AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 44
AD9739BBCRL
Manufacturer Part Number
AD9739BBCRL
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBCRL
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD9739
Operation in Master Mode
Setting Register 0x10, Bit 5 high sets the controller to master
mode. This enables the sync logic to enter an initialization
phase that adjusts the SYNC_OUT_x delay. By moving the
SYNC_OUT_x delay, the SYNC_IN_x sampling point is moved
and the edge transitions of Phase 0 and Phase 1 clocks can be
determined. After the edges are found, the SYNC_OUT_x delay
line is adjusted such that the SYNC_IN_x sampling point is
now placed in the center, away from the edge transitions, as
shown in Figure 93.
The sync controller also attempts to automatically select a phase
for the SYNC_OUT_x signal that is closest to the DCI. This
operation is performed to eliminate the arbitrary phase
relationship of the clock divider upon power-up. After the
SYNC_OUT_x delay is set and the phase is determined, the
master performs a clock divider phase rotation and enters
tracking mode.
WHERE:
T[N] = (EDGE1[N] + EDGE2[N]) >> 1
S[N] = SYNC_IN[N]
STEP SIZE
TARGET
ACTUAL
Figure 94. Synchronization Controller Track Mode Computation Block Diagram
T[N]
X[N]
S[N]
CONTROLLER
DIFF
SYNC TRACK DELAY
DIFFERENCE ERROR
CLK PHASE1
CLK PHASE0
SYNC_IN_x
Rev. 0 | Page 44 of 56
CLK
S[N]
SYNC TRACK
DELAY
DELAY
GOT E
GOT EDGE1
GOT SYNC
In tracking mode, the master cycles the sync track delay line
and stores the delay values for the first phase edge, the SYNC_IN_x
edge, and the second phase edge. These signals are only stored
internally and are not accessible via the SPI. Ideally, the
SYNC_IN_x position is exactly between two phases. The con-
troller automatically adjusts the SYNC_OUT_x delay to keep
the SYNC_IN_x edge centered. This operation is continuously
performed in the background, and the SYNC_OUT_x delay line
is adjusted to maintain proper positioning. The controller loop
is shown in Figure 94.
DGE2
SYNC_IN_x
±
PHASE 0
PHASE 1
FF
FF
FF
STEP SIZE
Figure 93. Optimal Placement of SYNC_IN_X
K
= 1
= 1
= 1
Y[N]
COMPUTED
RESULT