AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 29
AD9739BBCRL
Manufacturer Part Number
AD9739BBCRL
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBCRL
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 11. Power-Down Register Bit Descriptions
Bit Name
LVDS_DCO_PD
LVDS_RCVR_PD
CLK_REC_PD
DAC_BIAS_PD
Table 12. Controller Clock Disable Register (Register 0x02)
Register
Name
CNT_CLK_Dis
1
Table 13. Controller Clock Disable Register Bit Descriptions
Bit Name
CLKGEN_PD
REC_CNT_CLK
MU_CNT_CLK
Table 14. IRQ Registers (Register 0x03, Register 0x04)
Register
Name
IRQ_En
IRQ_Req
1
Table 15. IRQ Register Bit Descriptions
Bit Name
SYNC_LST_EN
SYNC_LCK_EN
MULST_EN
MULCK_EN
RCV_LST_EN
RCV_LCK_EN
SYNC_LST_IRQ
SYNC_LCK_IRQ
MULST_IRQ
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
Address
0x03
0x04
Read/Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
Address
0x02
Read/write
Read/write
Read/Write
Read/write
Read/write
03
04
1
Read/Write
Read/write
Read/write
Read/write
02
Bit 7
N/A
N/A
1
Description
0: reset SYNC_LST_IRQ and disable future SYNC_LST_IRQ.
1: enable SYNC_LST_IRQ request.
0: reset SYNC_IRQ and disable future SYNC_LCK_IRQ.
1: enable SYNC_IRQ request.
0: reset MULST_IRQ and disable future MULST_IRQ.
1: enable MULST_IRQ request.
0: reset MULCK_IRQ and disable future MULCK_IRQ.
1: enable the MULCK_IRQ request.
0: reset the RCVLST_IRQ and disable future RCVLST_IRQ.
1: enable the RCVLST_IRQ request.
0: reset the RCV_IRQ interrupt and disable future MULCK_IRQ.
1: enable RCV_IRQ request.
0: the sync controller has not lost lock.
1: the sync controller has lost lock and an interrupt has occurred.
0: the sync controller is unlocked.
1: the sync controller has achieved lock and an interrupt has occurred.
0: the mu controller has not lost lock.
1: the mu controller has lost lock and an interrupt has occurred.
Bit 7
N/A
Bit 6
N/A
N/A
Description
0: clocks enabled.
1: clocks disabled.
0: clock to LVDS receiver controller disabled.
1: clock to LVDS receiver controller enabled.
0: clock to mu controller disabled.
1: clock to mu controller enabled.
Description
0: DCO enabled.
1: DCO disabled.
0: LVDS receiver enabled.
1: LSB receiver powered down.
0: internal clock receiver enabled.
1: internal clock receiver powered down.
0: DAC bias circuitry enabled.
1: DAC bias circuitry powered down.
Bit 5
SYNC_LST_EN
SYNC_LST_IRQ
Bit 6
N/A
Bit 5
N/A
Bit 4
SYNC_LCK_EN
SYNC_LCK_IRQ
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Bit 4
N/A
Bit 3
MULST_EN
MULST_IRQ
Bit 3
CLKGEN_PD
Bit 2
MULCK_EN
MULCK_IRQ
Bit 2
N/A
Bit 1
RCV_LST_EN
RCVLST_IRQ
Bit 1
REC_CNT_CLK
Reset Value for
Write Register
0
0
0
0
Reset Value for
Write Register
0
0
0
Reset Value for
Write Register
0
0
0
0
0
0
0
0
0
Bit 0
RCV_LCK_EN
RCVLCK_IRQ
Bit 0
MU_CNT_CLK
AD9739