AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 4
AD9739BBCRL
Manufacturer Part Number
AD9739BBCRL
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBCRL
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD9739
DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
link, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS
LVDS CLOCK INPUT
LVDS CLOCK OUTPUT
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
SERIAL PERIPHERAL INTERFACE
(DB0[13:0]P, DB0[13:0]N, DB1[13:0]P, DB1[13:0]N) DB+ = V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate
LVDS Minimum Data Valid Period (t
Input Capacitance
(DCI_P, DCI_N) DCI_P = V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
Maximum Clock Rate
(DCO_P, DCO_N) DCO_P = V
Output Voltage High, V
Output Voltage Low, V
Output Differential Voltage, |V
Output Offset Voltage, V
Output Impedance, Single-Ended, R
R
Change in |V
Change in V
Output Current, Driver Shorted to Ground, I
Output Current, Drivers Shorted Together, I
Power-Off Output Leakage, |I
Maximum Clock Rate
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
Maximum Clock Rate (f
Minimum Pulse Width High, t
Minimum Pulse Width Low, t
Minimum SDIO and CS to SCLK Setup, t
Minimum SCLK to SDIO Hold, t
Maximum SCLK to Valid SDIO and SDO, t
Minimum SCLK to Invalid SDIO and SDO, t
O
VDD = 1.8 V ± 5%
VDD = 1.89 V ± 5%
Mismatch Between A and B, ∆RO
OS
OD
Between 0 and 1, ∆V
| Between 0 and 1, |ΔV
OA
IA
IA
OA
SCLK
OS
or V
or V
or V
IA
or V
, DCI_N = V
, 1/t
OA
IB
IB
OB
PWL
XA
OB
PWH
IDTH
IDTH
, DCO_N = V
IDTHH
IDTHH
OD
SCLK
DH
|, |I
|
)
XB
– V
− V
OS
MDE
|
O
OD
IB
IDTHL
IDTHL
)
|
DS
IN
IN
DV
OB
DNV
SAB
SA
100 Ω Termination
, I
SB
FS
= 20 mA. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range
IA
, DB−= V
Rev. 0 | Page 4 of 56
IB
Min
825
−100
80
1250
825
−100
80
625
1025
150
1150
40
625
800
800
20
20
Typ
20
1.2
20
200
100
1.8
900
10
5
20
5
Max
1575
+100
120
344
1575
+100
120
1375
250
1250
140
10
25
25
20
4
10
2400
2500
20
Unit
mV
mV
mV
Ω
MSPS
ps
pF
mV
mV
mV
Ω
MHz
mV
mV
mV
mV
Ω
%
mV
mV
mA
mA
mA
MHz
V
mV
MSPS
MSPS
MHz
ns
ns
ns
ns
ns
ns