AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 31
AD9739BBCRL
Manufacturer Part Number
AD9739BBCRL
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBCRL
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 21. LVDS Control/Status Register Bit Descriptions
Bit Name
HNDOFF_CHK_RST
LVDS_Bias[1:0]
HNDOFF_Fall[3:0]
HNDOFF_Rise[3:0]
SUP/HLD_Edge1
DCI_PHS3
DCI_PHS1
DCI_PRE_PH2
DCI_PRE_PH0
DCI_PST_PH2
DCI_PST_PH0
SUP/HLD_SYNC
SUP/HLD_Edge0
SYNC_SAMP1
SYNC_SAMP0
LVDS1_HI
LVDS1_LO
LVDS0_HI
LVDS0_LO
Read/Write
Read/write
Read/write
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Description
0: default. Bit is in the inactive state.
1: resets the handoff errors in Register 0x0B.
0x0: 360 μA bias current.
0x1: 460 μA bias current.
0x2: 560 μA bias current
0x3: 660 μA bias current.
0: there are no timing violations in the falling edges between the delay lines.
1: there is a timing violation in the falling edges between the delay lines.
0: there are no timing violations in the rising edges between the delay lines.
1: there is a timing violation in the rising edges between the delay lines.
Sample second phase of clock divider with setup/hold delay line.
0: divider phases aligned correctly.
1: divider phases aligned incorrectly.
0: divider phases aligned incorrectly.
1: divider phases aligned correctly.
0: the DCI signal is aligned with the Phase 2 edge.
1: the DCI signal is slightly before the Phase 2 edge.
0: the DCI signal is aligned with the Phase 0 edge.
1: the DCI signal is slightly before the Phase 0 edge.
0: the DCI signal is aligned with the Phase 2 edge.
1: the DCI signal is slightly after the Phase 2 edge.
0: the DCI signal is aligned with the Phase 0 edge.
1: the DCI signal is slightly after the Phase 0 edge.
Sample SYNC_IN with setup/hold delay line (should be between the first phase
and the second phase).
Sample first phase of clock divider with setup/hold delay line.
SYNC_IN sample of clock divider Phase 1.
SYNC_IN sample of clock divider Phase 0.
One or more LVDS inputs on Port 1 are above the input voltage limits of the IEEE
reduce link specification.
One or more LVDS inputs on Port 1 are below the input voltage limits of the IEEE
reduce link specification.
One or more LVDS inputs on Port 0 are above the input voltage limits of the IEEE
reduce link specification.
One or more LVDS inputs on Port 0 are below the input voltage limits of the IEEE
reduce link specification.
Rev. 0 | Page 31 of 56
Reset Value for
Write Register
0x00
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD9739