AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 26

• Manufacturer Part Number: AD9739BBCRL
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCRL

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9739
MSB/LSB TRANSFERS
The AD9739 serial port can support both MSB-first and LSB-
first data formats. This functionality is controlled by LSB/MSB
at Register 0x00, Bit 6. The default is MSB first (LSB/MSB = 0).
When LSB/MSB = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least
significant bit.
When LSB/MSB = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most
significant bit.
SERIAL PORT CONFIGURATION
The AD9739 serial port configuration is controlled by Register
0x00, Bits[7:5]. Note that the configuration changes immediately
upon writing to the last bit of the register. When setting the
software reset (Register 0x00, Bit 5), all registers are set to their
default values except Register 0x00, which remains unchanged.
In the event of unexpected programming sequences, the
AD9739 SPI can become inaccessible. For example, if user code
inadvertently changes the LSB/MSB bit, the following bits
experience unexpected results. The SPI can be returned to a
known state by writing an incomplete byte (1 to 7 bits) of all 0s
followed by three bytes of 0x00. This returns to the MSB-first
instructions (Register 0 x00 = 0x00) so that the device can be
reinitialized.
SCLK
SDIO
SDO
SCLK
SDIO
CS
CS
Figure 74. Serial Register Interface Timing, MSB-First Write
Figure 75. Serial Register Interface Timing, MSB-First Read
R/W A6 A5 A4 A3
R/W A6 A5 A4 A3
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A2 A1 A0
A2 A1 A0 D7
D7
D7
D6
D6
N
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D6
N
N
D5
D5
N
D5
N
N
N
D3
D3
D3
0
0
D2
0
D2
D2
0
0
0
D1
D1
D1
0
0
0
D0
D0
D0
0
0
0
Rev. 0 | Page 26 of 56
After the last instruction bit is written to the SDIO pin, the
driving signal must be set to a high impedance in time for the
bus to turn around. The serial output data from the AD9739 is
enabled by the falling edge of SCLK. This causes the first output
data bit to be shorter than the remaining data bits, as shown in
Figure 79. To assure proper reading of data, read the SDIO or
SDO pin prior to changing the SCLK from low to high. Due to
the more complex multibyte protocol, multiple AD9739 devices
cannot be daisy-chained on the SPI bus. Multiple DACs should
be controlled by independent CS signals.
SCLK
SCLK
SDIO
SCLK
SCLK
SDIO
SDIO
SDO
SDIO
CS
CS
CS
CS
I1
Figure 76. Serial Register Interface Timing, LSB-First Write
Figure 77. Serial Register Interface Timing, LSB-First Read
R/W
Figure 78. Timing Diagram for an SPI Register Write
Figure 79. Timing Diagram for an SPI Register Read
R/W
I0
INSTRUCTION BIT 7
A0 A1 A2 A3 A4 A5 A6
t
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A0 A1 A2 A3 A4 A5 A6
t
DS
DS
t
PWH
t
DH
t
D7
SCLK
t
PWL
INSTRUCTION BIT 6
D0
D0
D0
t
0
DNV
DATA TRANSFER CYCLE
D1
D1
DATA TRANSFER CYCLE
D1
0
0
0
D2
D2
D6
D2
0
0
0
D4
D4
D4
t
DV
N
N
0
D5
D5
D5
N
N
N
D6
D6
D6
N
N
N
D7
D7
D5
D7
N
N
N