AD9753ASTZRL Analog Devices Inc, AD9753ASTZRL Datasheet - Page 10

• Manufacturer Part Number: AD9753ASTZRL
• Description: 12-Bit, 300 MSPS TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9753ASTZRL

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9753-EB - BOARD EVAL FOR AD9753
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9753
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9753. The
AD9753 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, I
array is divided into 31 equal sources that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSBs are a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
All of the current sources are switched to one of the two
outputs (i.e., I
switches. The switches are based on a new architecture that
drastically improves distortion performance. This new switch
architecture reduces various timing errors and provides matching
complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9753 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V band gap voltage refer-
ence, and a reference control amplifier.
The full-scale output current is regulated by the reference control
amplifier and can be set from 2 mA to 20 mA via an external
resistor, R
the reference control amplifier and voltage reference V
the reference current I
current sources with the proper scaling factor. The full-scale
current, I
OUTFS
SET
0.1 F
. The external resistor, in combination with both
OUTA
, is 32 times the value of I
R
2k
SET
or I
REF
OUTB
, which is replicated to the segmented
REFIO
FSADJ
DCOM
1.2V REF
) via PMOS differential current
ACOM
AD9753
3.0V TO 3.6V
DVDD
PMOS CURRENT
SOURCE ARRAY
REF
.
AVDD
PORT 1 LATCH
OUTFS
Figure 3. Simplified Block Diagram
DB0 – DB11
DIGITAL DATA INPUTS
. The
SWITCHES FOR
REFIO
DB0 TO DB11
SEGMENTED
DAC LATCH
2 –1 MUX
, sets
PORT 2 LATCH
DB0 – DB11
–10–
DAC
REFERENCE OPERATION
The AD9753 contains an internal 1.20 V band gap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an input or output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1 µF capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier
with an input bias current less than 100 nA should be used. An
example of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO,
as shown in Figure 5. The external reference may provide either
a fixed reference voltage to enhance accuracy and drift perfor-
mance or a varying reference voltage for gain control. Note
that the 0.1 µF compensation capacitor is not required since
the internal reference is overdriven, and the relatively high input
impedance of REFIO minimizes any loading of the external
reference.
ADDITIONAL
EXTERNAL
DIV0
Figure 5. External Reference Configuration
LOAD
Figure 4. Internal Reference Configuration
CIRCUITRY
REFERENCE
EXTERNAL
DIV1
REFERENCE
EXTERNAL
OPTIONAL
PLL
AVDD
BUFFER
PLLLOCK
I
REF
I
I
I
0.1 F
REF
PLLVDD
CLKVDD
CLK+
CLK–
CLKCOM
RESET
LPF
OUTA
OUTB
2k
V
REFIO
FSADJ
2k
DIFF
1.2V REF
= V
REFIO
FSADJ
REFERENCE
OUT
AD9753
R
50
SECTION
V
OUT
1.2V REF
LOAD
A – V
REFERENCE
B
AD9753
SECTION
OUT
B
CURRENT
SOURCE
ARRAY
R
50
V
OUT
LOAD
AVDD
CURRENT
SOURCE
A
ARRAY
AVDD
REV. B