AD9753ASTZRL Analog Devices Inc, AD9753ASTZRL Datasheet - Page 14

• Manufacturer Part Number: AD9753ASTZRL
• Description: 12-Bit, 300 MSPS TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9753ASTZRL

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9753-EB - BOARD EVAL FOR AD9753
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9753
Substituting the values of I
expressed as
These last two equations highlight some of the advantages of
operating the AD9753 differentially. First, the differential opera-
tion will help cancel common-mode error sources associated
with I
Second, the differential code-dependent current and subsequent
voltage, V
output (i.e., V
power to the load.
Note that the gain drift temperature performance for a single-
ended (V
AD9753 can be enhanced by selecting temperature tracking
resistors for R
ship, as shown in Equation 8.
ANALOG OUTPUTS
The AD9753 produces two complementary current outputs,
I
differential operation. I
complementary single-ended voltage outputs, V
via a load resistor, R
8 in the DAC Transfer Function section. The differential voltage,
V
verted to a single-ended voltage via a transformer or differential
amplifier configuration. The ac performance of the AD9753 is
optimum and specified using a differential transformer-coupled
output in which the voltage swing at I
to ± 0.5 V. If a single-ended unipolar output is desirable, I
should be selected as the output, with I
The distortion and noise performance of the AD9753 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more significant
as the frequency content of the reconstructed waveform increases.
This is due to the first order cancellation of various dynamic
common-mode distortion mechanisms, digital feedthrough,
and noise.
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of I
tary, they become additive when processed differentially. A
properly selected transformer will allow the AD9753 to provide
the required power and voltage levels to different loads. Refer to
the Applying the AD9753 Output Configurations section for
examples of various output configurations.
The output impedance of I
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V
OUTA
DIFF
, existing between V
OUTA
and I
OUTA
OUTA
V
(32 R
DIFF
DIFF
and I
OUTB
and V
LOAD
OUTA
, is twice the value of the single-ended voltage
and V
LOAD
= {(2 DAC CODE – 4095)/4096} ×
OUTB
, that may be configured for single-ended or
OUTB
and R
or V
/R
LOAD
OUTB
such as noise, distortion, and dc offsets.
SET
) due to the nature of a PMOS device.
OUTB
OUTA
, as described by Equations 5 through
SET
) or differential output (V
) × V
OUTA
OUTA
OUTA
), thus providing twice the signal
due to their ratiometric relation-
OUTA
and I
REFIO
and V
and I
, I
and I
OUTB,
OUTB
OUTA
OUTB
OUTA
OUTB
OUTB
OUTB
and I
can be converted into
and I
is determined by the
, can also be con-
and I
grounded.
OUTA
are complemen-
REF
OUTB
OUTB
, V
and V
DIFF
DIFF
is limited
can be
) of the
OUTB
can be
OUTA
(8)
,
–14–
As a result, maintaining I
via an I–V op amp configuration will result in the optimum dc
linearity. Note that the INL/DNL specifications for the AD9753
are measured with I
via an op amp.
I
pliance range that must be adhered to in order to achieve optimum
performance. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9753.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.25 V for an I
= 2 mA. The optimum distortion performance for a single-
ended or differential output is achieved when the maximum
full-scale signal at I
Applications requiring the AD9753’s output (i.e., V
or V
R
will adversely affect the AD9753’s linearity performance and
subsequently degrade its distortion performance.
DIGITAL INPUTS
The AD9753’s digital inputs consist of two channels of 14 data
input pins each and a pair of differential clock input pins. The
12-bit parallel data inputs follow standard straight binary coding
where DB13 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). I
current when all data bits are at Logic 1. I
complementary output with the full-scale current split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. With the PLL active or disabled, the DAC
output is updated twice for every input latch rising edge, as
shown in Figures 7 and 11. The AD9753 is designed to support
an input data rate as high as 150 MSPS, giving a DAC output
update rate of 300 MSPS. The setup-and-hold times can also
be varied within the clock cycle as long as the specified mini-
mum times are met. Best performance is typically achieved
when the input data transitions on the falling edge of a 50%
duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
V
(DVDD) or
The internal digital circuitry of the AD9753 is capable of oper-
ating over a digital supply range of 3.0 V to 3.6 V. As a result,
the digital inputs can also accommodate TTL levels when DVDD
is set to accommodate the maximum high level voltage of the
TTL drivers V
ensures proper compatibility with most TTL logic families.
Figure 14 shows the equivalent digital input circuit for the data
and clock inputs.
OUTA
LOAD
THRESHOLD
OUTB
and I
accordingly. Operation beyond this compliance range
) to extend its output compliance range should size
OUTB
, set to approximately half the digital positive supply
OH
also have a negative and positive voltage com-
(max). A DVDD of 3.0 V to 3.6 V typically
V
OUTA
OUTA
THRESHOLD
OUTFS
and I
OUTA
and I
OUTA
= 20 mA to 1.00 V for an I
OUTFS
OUTB
and/or I
OUTB
= DVDD/2 (± 20%)
produces a full-scale output
maintained at virtual ground
. It degrades slightly from its
does not exceed 0.5 V.
OUTB
at a virtual ground
OUTB
produces a
OUTA
REV. B
OUTFS
and/