AD9753ASTZRL Analog Devices Inc, AD9753ASTZRL Datasheet - Page 13

• Manufacturer Part Number: AD9753ASTZRL
• Description: 12-Bit, 300 MSPS TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9753ASTZRL

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9753-EB - BOARD EVAL FOR AD9753
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERLEAVED (2 ) MODE WITH PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 11. A clock at the output update data
rate (2× the input data rate) must be applied to the CLK inputs.
Internal dividers then create the internal 1× clock necessary for
the input latches. Although the input latches are updated on the
rising edge of the delayed internal 1× clock, the setup-and-hold
times given in the Digital Specifications table are with respect to
the rising edge of the external 2× clock. With the PLL disabled,
a load-dependent delayed version of the 1× clock is present at
the PLLLOCK pin. This signal can be used to synchronize the
external data.
Updates to the data at input Ports 1 and 2 should be synchro-
nized to the specific rising edge of the external 2× clock that
corresponds to the rising edge of the 1× internal clock, as shown
in Figure 11. To ensure synchronization, a Logic 1 must be
momentarily applied to the RESET pin. Doing this and return-
ing RESET to Logic 0 brings the 1× clock at PLLLOCK to a
Logic 1. On the next rising edge of the 2× clock, the 1× clock
will go to Logic 0. On the second rising edge of the 2× clock,
the 1× clock (PLLLOCK) will again go to Logic 1, as well as
update the data in both of the input latches. The details of this
are shown in Figure 12.
For proper synchronization, sufficient delay must be present
between the time RESET goes low and the rising edge of the 2×
clock. RESET going low must occur either at least t
the rising edge of the 2× clock, or t
first case, the immediately occurring CLK rising edge will
cause PLLLOCK to go low. In the second case, the next
CLK rising edge will toggle PLLLOCK.
REV. B
Figure 12. RESET Function Timing with PLL Disabled
@ PLLLOCK
EXTERNAL
EXTERNAL
INTERNAL
DATA IN
DELAYED
PORT 1
PORT 2
Figure 11. Timing Requirements, Interleaved (2 × )
Mode with PLL Disabled
1
1
2
CLK
CLK
CLK
EXTERNAL
2
PLLLOCK
CLOCK
RESET
t
DATA X
DATA Y
I
OUTA
S
ON THESE EDGES
INPUT LATCHES
t
OR I
t
t
H
DATA ENTERS
D
LPW
t
RS
OUTB
= 0.2ns
t
PD
DATA ENTERS
INPUT LATCHES
ON THIS EDGE
RH
DATA X
t
RH
ns afterwards. In the
= 1.2ns
t
PD
RS
DATA Y
ns before
–13–
NONINTERLEAVED MODE WITH PLL DISABLED
If the data at only one port is required, the AD9753 interface can
operate as a simple double buffered latch with no interleaving.
On the rising edge of the 1× clock, input latch 1 or 2 is updated
with the present input data (depending on the state of DIV0/
DIV1). On the next rising edge, the DAC latch is updated and a
time t
represents the AD9753 timing in this mode.
DAC TRANSFER FUNCTION
The AD9753 provides complementary current outputs, I
and I
I
I
current output appearing at I
both the input code and I
where DAC CODE = 0 to 4095 (i.e., decimal representation).
As mentioned previously, I
current, I
V
where
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, I
should be directly connected to matching resistive loads, R
that are tied to analog common, ACOM. Note that R
represent the equivalent load resistance seen by I
as would be the case in a doubly terminated 50 Ω or 75 Ω cable.
The single-ended voltage output appearing at the I
I
Note that the full-scale values of V
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
OUTFS
OUTB
OUTB
REFIO
I
I
I
I
OUTB
, the complementary output, provides no current. The
OUTA
OUTB
OUTFS
REF
PD
nodes is simply
Figure 13. Timing Requirements, Noninterleaved
Mode with PLL Disabled
, when all bits are high (i.e., DAC CODE = 4095), while
, and an external resistor R
V
V
PORT 1 OR
1
later, the DAC output reflects this change. Figure 13
OUTA
OUTB
= V
V
. I
DATA IN
REF
PORT 2
CLOCK
= (DAC CODE/4096) × I
= (4095 – DAC CODE)/4096 × I
DIFF
OUTA
= 32 × I
, which is nominally set by a reference voltage,
REFIO
= I
= I
= (I
will provide a near full-scale current output,
OUTA
OUTB
/R
I
OUTA
OUTA
REF
SET
t
S
× R
× R
OR I
OUTFS
– I
t
OUTFS
LOAD
t
OUTB
LOAD
H
LPW
OUTB
OUTA
and can be expressed as
is a function of the reference
SET
) × R
OUTA
and I
. It can be expressed as
OUTFS
LOAD
and V
XX
OUTB
t
PD
OUTB
OUTFS
is a function of
AD9753
OUTA
PORT 1 OR
DATA OUT
OUTA
PORT 2
OUTA
should not
LOAD
and I
or I
and
OUTA
OUTB
may
OUTB
LOAD
(1)
(2)
(3)
(4)
(5)
(6)
(7)
,