AD9753ASTZRL Analog Devices Inc, AD9753ASTZRL Datasheet - Page 7

• Manufacturer Part Number: AD9753ASTZRL
• Description: 12-Bit, 300 MSPS TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9753ASTZRL

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9753-EB - BOARD EVAL FOR AD9753
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Specified as the maximum change from the ambient (25°C)
value to the value at either T
drift, the drift is reported in ppm of full-scale range (FSR) per
degree Celsius. For reference drift, the drift is reported in ppm
per degree Celsius.
REV. B
0.1 F
R
2k
SET
REFIO
FSADJ
DCOM
OUTB
OUTA
1.2V REF
, 0 mA output is expected when all
ACOM
, 0 mA output is expected when the
MIN
AD9753
DVDD
3.0V TO 3.6V
or T
PMOS CURRENT
SOURCE ARRAY
MAX
Figure 2. Basic AC Characterization Test Setup
AVDD
. For offset and gain
PORT 1 LATCH
DB0 – DB11
DIGITAL DATA INPUTS
(FOR DATA RETIMING)
AWG2021 w/OPTION 4
TEKTRONIX DG2020
PULSE GENERATOR
SWITCHES FOR
DB0 TO DB11
LECROY 9210
SEGMENTED
DAC LATCH
2 –1 MUX
OR
PORT 2 LATCH
DB0 – DB11
PLL DISABLED
DAC
–7–
CIRCUITS
T1-1T
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Adjacent Channel Power Ratio (ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
MINI
CLK+
PLL ENABLED
CIRCUITRY
CLK–
PLL
PLLLOCK
1k
HP8644
SIGNAL
GENERATOR
I
I
PLLVDD
CLKVDD
RESET
LPF
CLKCOM
DIV0
DIV1
OUTA
OUTB
1k
3.0V TO 3.6V
50
50
CIRCUITS
T1-1T
MINI
TO ROHDE &
SCHWARZ
FSEA30
SPECTRUM
ANALYZER
AD9753