AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 15

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYNC PROCESSING
The inputs of the sync processing section of the AD9983A are
combinations of digital Hsyncs and Vsyncs, analog sync-on-
green, or sync-on-Y signals, and an optional external coast
signal. From these signals it generates a precise, jitter-free clock
from its PLL; an odd/even field signal; HSOUT and VSOUT
signals; a count of Hsyncs per Vsync; and a programmable
SOGOUT. The main sync processing blocks are the sync slicer,
sync separator, Hsync filter, Hsync regenerator, Vsync filter, and
coast generator.
• The sync slicer extracts the sync signal from the green
• The sync separator’s task is to extract Vsync from the
• The Hsync filter is used to eliminate any extraneous pulses
graphics or luminance video signal that is connected to the
SOGINx input and outputs a digital composite sync.
composite sync signal, which can come from either the sync
slicer or the HSYNCx inputs.
from the HSYNCx or SOGINx inputs, outputting a clean,
low jitter signal that is appropriate for mode detection and
clock generation.
EXTCK/COAST
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
ACTIVITY
ACTIVITY
ACTIVITY
ACTIVITY
DETECT
DETECT
DETECT
DETECT
AD9983A
SYNC SLICER
SYNC SLICER
POLARITY
POLARITY
POLARITY
POLARITY
DETECT
DETECT
DETECT
DETECT
ACTIVITY
ACTIVITY
DETECT
DETECT
MUX
MUX
MUX
Figure 8. Sync Processing Block Diagram
CHANNEL
SELECT
VSYNC FILTER
Rev. 0 | Page 15 of 44
PROCESSOR
SYNC
AND
SELECT
MUX
HSYNC
MUX
COAST
•
•
•
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics or luminance video signal that is connected
to the SOG input. The sync signal is extracted in a two step
process. First, the SOG input is clamped to its negative peak,
(typically 0.3 V below the black level). Next, the signal goes to a
comparator with a variable trigger level (set by Register 0x1D,
Bits[7:3]), but nominally 0.128 V above the clamped level. The
sync slicer output is a digital composite sync signal containing
both Hsync and Vsync information (see Figure 9).
The Hsync regenerator is used to recreate a clean, although
not low jitter, Hsync signal that can be used for mode
detection and counting Hsyncs per Vsync.
The Vsync filter is used to eliminate spurious Vsyncs,
maintain a stable timing relationship between the Vsync and
Hsync output signals, and generate the odd/even field output.
The coast generator creates a robust coast signal that
allows the PLL to maintain its frequency in the absence of
Hsync pulses.
REG 0x26, 0x27
HSYNC/VSYNC
HSYNC
FILTERED
COUNTER
GENERATOR
PLL CLOCK
HSYNC
REGENERATOR
HSYNC FILTER
AND
REGENERATED
HSYNC
MUX
POLARITY
POLARITY
POLARITY
POLARITY
SET
SET
SET
SET
SOGOUT
VSOUT/A0
O/E FIELD
HSOUT
DATACK
AD9983A