AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 23

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2-WIRE SERIAL REGISTER MAP
The AD9983A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 14. Control Register Map
Hex
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Read/Write,
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:4
7:6
5:3
2
7:3
6:0
7:0
6:0
7:0
6:0
7:0
7:0
7
7:0
7
7:0
7
7:0
Bits
Default
Value
0110 1001
1101 ****
01** ****
**00 1***
**** *0**
1000 0***
*100 0000
0000 0000
*100 0000
0000 0000
*100 0000
0000 0000
0100 0000
0*** ****
0100 0000
0*** ****
0100 0000
0*** ****
0010 0000
Register Name
Chip Revision
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Red Gain MSB
Green Gain MSB
Blue Gain MSB
Red Offset MSB
Red Offset LSB
Green Offset MSB
Green Offset LSB
Blue Offset MSB
Blue Offset LSB
Sync Separator
Threshold
Rev. 0 | Page 23 of 44
An 8-bit register that represents the silicon revision level.
Description
This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock).
LSBs of the PLL Divider Word. Links to the PLL Div MSB to make a
12-bit register.
VCO Range. Selects VCO frequency range. (See PLL section).
Charge Pump Current. Varies the current that drives the low-pass
filter. (See PLL section).
External Clock Enable.
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32).
7-Bit Red Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
Must be written to 0x00 following a write of Reg. 0x05 for proper
operation.
7-Bit Green Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
Must be written to 0x00 following a write of Reg. 0x07 for proper
operation.
7-Bit Blue Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
Must be written to 0x00 following a write of Reg. 0x09 for proper
operation.
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.
Linked with Reg. 0x0B to form the 9-bit red offset that controls the
dc offset (brightness) of the red channel in auto-offset mode.
8-Bit MSB of the Green Channel Offset Control. Controls the dc
offset (brightness) of each respective channel. Bigger values
decrease brightness.
Linked with Reg. 0x0D to form the 9-bit green offset that controls
the dc offset (brightness) of the green channel in auto-offset mode.
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.
Linked with Reg. 0x0F to form the 9-bit blue offset that controls the
dc offset (brightness) of the blue channel in auto-offset mode.
This register sets the threshold of the sync separator’s digital
comparator.
1
2
2
2
1
1
1
1
AD9983A