AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 9

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mnemonic
REFLO, REFHI
FILT
HSOUT
VSOUT/A0
SOGOUT
O/E FIELD
SDA
SCL
RED [7:0]
GREEN [7:0]
BLUE [7:0]
DATACK
V
V
PV
DAV
GND
D
DD
D
(1.8 V)
(1.8 V to 3.3 V)
(1.8 V)
DD
(1.8 V)
Function
Input Amplifier Reference
External Filter Connection
Horizontal Sync Output
Vertical Sync Output
Serial Port Address Input 0
Sync-On-Green Slicer
Output
Odd/Even Field Bit for
Interlaced Video
Serial Port Data I/O
Serial Port Data Clock
Data Output, Red Channel
Data Output, Green Channel
Data Output, Blue Channel
Data Clock Output
Main Power Supply
Digital Output Power Supply
Clock Generator Power
Supply
Digital Input Power Supply
Ground
Description
REFLO and REFHI are connected together through a 10 μF capacitor. These are used for
stability in the input ADC circuitry. See Figure 6.
For proper operation, the pixel clock generator PLL requires an external filter. Connect the
filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics
on this node. For more information, see the PCB Layout Recommendations section.
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and
duration of this output can be programmed via serial bus registers. By maintaining
alignment with DATACK and Data, data timing with respect to Hsync can always be
determined.
Pin shared with A0, serial port address. This can be either a separated Vsync from a
composite signal or a direct pass through of the Vsync signal. The polarity of this output can
be controlled via a serial bus bit. The placement and duration in all modes can be set by the
graphics transmitter or the duration can be set by Register 0x14 and Register 0x15. This pin
is shared with the A0 function, which does not affect Vsync Output functionality. For more
details on A0, see the description in the Serial Control Port section.
Pin shared with VSOUT. This pin selects the LSB of the serial port device address,
allowing two Analog Devices parts to be on the same serial bus. A high impedance
external pull-up resistor enables this pin to be read at power-up as 1, or a high
impedance, external pull-down resistor enables this pin to be read at power-up as a 0
and not interfere with the VSOUT functionality.
This pin outputs one of four possible signals (controlled by Register 0x1D, Bits[1:0]): raw
SOG, raw Hsync, regenerated Hsync from the filter, or the filtered Hsync. See Figure 8 to
view how this pin is connected. Other than slicing off SOG, the output from this pin
gets no additional processing on the AD9983A. Vsync separation is performed via the
sync separator.
This output will identify whether the current field (in an interlaced signal) is odd or even.
Data I/O for the I
Clock for the I
The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
This is the main clock output signal used to strobe the output data and HSOUT into
external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6].
Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock
and 2× frequency pixel clock). They are produced either by the internal PLL clock
generator or EXTCK and are synchronous with the pixel sampling clock. The fourth
option for the data clock output is an internally generated 1⁄2x pixel clock.
The sampling time of the internal pixel clock can be changed by adjusting the phase
register (Register 0x04). When this is changed, the pixel related DATACK timing is also
shifted. The data, DATACK, and HSOUT outputs are all moved so that the timing
relationship among the signals is maintained.
These pins supply power to the main elements of the circuit. They should be as quiet
and filtered as possible.
A large number of output pins (up to 29) switching at high speed (up to 140 MHz)
generates a lot of power supply transients (noise). These supply pins are identified
separately from the V
transferred into the sensitive analog circuitry. If the AD9983A is interfacing with lower
voltage logic, V
compatibility.
The most sensitive portion of the AD9983A is the clock generation circuitry. These pins
provide power to the clock PLL and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.
This supplies power to the digital logic.
The ground return for all circuitry on-chip. It is recommended that the AD9983A be
assembled on a single solid ground plane, with careful attention to ground current paths.
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2
C serial port.
DD
2
C® serial port.
can be connected to a lower supply voltage (as low as 1.8 V) for
D
pins, so special care can be taken to minimize output noise
AD9983A