AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 35

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OUTPUT CONTROL
0x1F—Bits[7:5] Output Mode
These bits choose between three options for the output mode.
In 4:4:4 mode, RGB is standard. In 4:2:2 mode, YCbCr is
standard, which allows a reduction in the number of output
pins from 24 to 16. In 4:4:4 DDR output mode, the data is in
RGB mode, but changes on every clock edge. The power-up
default setting is 100.
Table 51. Output Mode
Output Mode
100
101
110
0x1F—Bit[4] Primary Output Enable
This bit places the primary output in active or high impedance
mode. The power-up default setting is 1.
Table 52. Primary Output Enable
Select
0
1
0x1F—Bit[3] Secondary Output Enable
This bit places the secondary output in active or high
impedance mode.
The secondary output is designated when using either 4:2:2 or
4:4:4 DDR. In these modes, the data on the blue output channel is
the secondary output while the output data on the red and green
channels are the primary output. Secondary output is always a
DDR YCbCr data mode. See the Output Formatter section and
Table 12. The power-up default setting is 0.
Table 53. Secondary Output Enable
Select
0
1
0x1F—Bits[2:1] Output Drive Strength
These two bits select the drive strength for all the high-speed
digital outputs (except VSOUT, A0, and the O/E field). Higher
drive strength results in faster rise/fall times and in general
makes it easier to capture data. Lower drive strength results in
slower rise/fall times and helps to reduce EMI and digitally
generated power supply noise. The power-up default setting is 10.
Table 54. Output Drive Strength
Output Drive
00
01
10
11
Result
Secondary output is in high impedance mode
Secondary output is enabled
Result
Low output drive strength
Medium low output drive strength
Medium high output drive strength
High output drive strength
Result
Primary output is in high impedance mode
Primary output is enabled
Result
4:4:4 RGB mode
4:2:2 YCbCr mode
4:4:4 DDR mode
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0x1F—Bit[0] Output Clock Invert
This bit allows inversion of the output clock. The power-up
default setting is 0.
Table 55. Output Clock Invert
Select
0
1
0x20—Bits[7:6] Output Clock Select
These bits allow selection of optional output clocks such as a
fixed 40 MHz clock, a 2× clock, a 90° phase-shifted clock, or the
normal pixel clock. The power-up default setting is 00.
Table 56. Output Clock Select
Select
00
01
10
11
0x20—Bit[5] Output High Impedance
This bit puts all outputs (except SOGOUT) in a high impedance
state. The power-up default setting is 0.
Table 57. Output High Impedance
Select
0
1
0x20—Bit[4] SOG High Impedance
This bit allows the SOGOUT pin to be placed in high impedance
mode. The power-up default setting is 0.
Table 58. SOGOUT High Impedance
Select
0
1
0x20—Bit[3] Field Output Polarity
This bit sets the polarity of the field output bit. The power-up
default setting is 1.
Table 59. Field Output Polarity
Select
0
1
Result
Normal outputs
All outputs (except SOGOUT) in high impedance mode
Result
Normal SOG output
SOGOUT pin is in high impedance mode
Result
Active low = even field; active high = odd field
Active low = odd field; active high = even field
Result
Noninverted pixel clock
Inverted pixel clock
Result
Pixel clock
90° phase-shifted pixel clock
2× pixel clock
40 MHz internal clock
AD9983A