ADSP-21368BBPZ-2A Analog Devices Inc, ADSP-21368BBPZ-2A Datasheet - Page 18

• Manufacturer Part Number: ADSP-21368BBPZ-2A
• Description: IC,DSP,32-BIT,CMOS,BGA,256PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21368BBPZ-2A

• Interface: DAI, DPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA Exposed Pad, 256-eBGA, 256-HBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 333MHz
• Mips: 333
• Device Input Clock Speed: 333MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: SBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21367/ADSP-21368/ADSP-21369
PACKAGE INFORMATION
The information presented in
the package branding for the ADSP-21367/ADSP-21368/
ADSP-21369 processors. For a complete listing of product avail-
ability, see
Table 9. Package Brand Information
ESD CAUTION
MAXIMUM POWER DISSIPATION
See Estimating Power Dissipation for ADSP-21368 SHARC Pro-
cessors (EE-299) for detailed thermal and power information
regarding maximum power dissipation. For information on
package thermal specifications, see
Page
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
#
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50.
Ordering Guide on Page
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Figure 4. Typical Package Brand
#yyww country_of_origin
S
a
ADSP-2136x
vvvvvv.x n.n
Field Description
Temperature Range
Package Type
RoHS Compliant Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliant Designation
Date Code
tppZ-cc
Figure 4
Thermal Characteristics on
Table 10
58.
provides details about
may cause perma-
Rev. E | Page 18 of 60 | July 2009
Table 10. Absolute Maximum Ratings
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 40 on Page 48
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
Parameter
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature Under Bias
VCO
• The product of CLKIN and PLLM must never exceed 1/2 of
Figure
specified in
f
(INDIV = 0).
VCO
(max) in
5). This PLL-based clocking minimizes the skew
Table
Table 13
under
13.
if the input divider is not enabled
Test Conditions
VDD
DDEXT
DDINT
)
)
)
Rating
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
–0.5 V to +3.8 V
–0.5 V to V
200 pF
–65 C to +150 C
125 C
for voltage refer-
DDEXT
+ 0.5 V