ADSP-21368BBPZ-2A Analog Devices Inc, ADSP-21368BBPZ-2A Datasheet - Page 29

• Manufacturer Part Number: ADSP-21368BBPZ-2A
• Description: IC,DSP,32-BIT,CMOS,BGA,256PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21368BBPZ-2A

• Interface: DAI, DPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA Exposed Pad, 256-eBGA, 256-HBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 333MHz
• Mips: 333
• Device Input Clock Speed: 333MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: SBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)
Table 23. SDRAM Interface Enable/Disable Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
t
For f
DSDC
ENSDC
DSDCC
ENSDCC
DSDCA
ENSDCA
CCLK
= 400 MHz (SDCLK ratio = 1:2.5).
Command Disable After CLKIN Rise
Command Enable After CLKIN Rise
SDCLK Disable After CLKIN Rise
SDCLK Enable After CLKIN Rise
Address Disable After CLKIN Rise
Address Enable After CLKIN Rise
COMMAND
COMMAND
SDCLK
SDCLK
CLKIN
ADDR
ADDR
Figure 18. SDRAM Interface Enable/Disable Timing
Rev. E | Page 29 of 60 | July 2009
1
t
t
t
t
t
ENSDCA
ENSDCC
t
DSDCC
DSDCA
ENSDC
DSDC
ADSP-21367/ADSP-21368/ADSP-21369
Min
4.0
3.8
2 × t
PCLK
– 4
Max
2 × t
8.5
9.2
4 × t
PCLK
PCLK
+ 3
Unit
ns
ns
ns
ns
ns
ns