ADSP-21368BBPZ-2A Analog Devices Inc, ADSP-21368BBPZ-2A Datasheet - Page 31

• Manufacturer Part Number: ADSP-21368BBPZ-2A
• Description: IC,DSP,32-BIT,CMOS,BGA,256PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21368BBPZ-2A

• Interface: DAI, DPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA Exposed Pad, 256-eBGA, 256-HBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 333MHz
• Mips: 333
• Device Input Clock Speed: 333MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: SBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
masters, accessing external memory space in asynchronous
Table 25. Memory Write
1
2
3
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) × t
ACK delay/setup: System must meet t
The falling edge of MSx is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
WWR
DDWR
WDE
ADDR
DATA
MSx
ACK
WR
RD
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulse Width
Data Setup Before WR High
Address Hold After WR Deasserted
Data Hold After WR Deasserted
WR High to WR, RD Low
Data Disable Before RD Low
WR Low to Data Enabled
t
DAAK
DAWL
t
WDE
, or t
t
DAAK
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t
1, 3
t
DSAK
2
1, 2
2
Rev. E | Page 31 of 60 | July 2009
Figure 20. Memory Write
t
DAWH
SDCLK
SDCLK
t
.
.
DDWH
Min
t
t
W – 1.3
t
H + 0.15
H + 0.02
t
2t
t
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
t
WW
SDCLK
– 3.1+ W
– 2.7
– 3.0+ W
– 1.5+ H
– 3.5
– 4.11
ADSP-21367/ADSP-21368/ADSP-21369
access mode. Note that timing for ACK, DATA, RD, WR, and
strobe timing parameters only applies to asynchronous access
mode.
Max
t
W – 4.9
t
DATRWH
SDCLK
– 9.7 + W
t
DWHD
t
WWR
t
DWHA
t
DDWR
DAAK
or t
DSAK
.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns