AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 26

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Enter SecSi
Command Sequence
The SecSi Sector region provides a secured
data area containing a random, sixteen-byte
electronic serial number (ESN). The system can
access the SecSi Sector region by issuing the
three-cycle Enter SecSi Sector command se-
quence. The device continues to access the
SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command se-
quence returns the device to normal operation.
Table 14, on page 29
data requirem ents for both comm and se-
quences. Note that the ACC function and unlock
bypass modes are not available when the de-
vice enters the SecSi Sector. See also
Sector (Secured Silicon) Flash Memory Region”
on page 20
Byte/Word Program Command Sequence
The system may program the device by word or
byte, depending on the state of the BYTE# pin.
Programming is a four-bus-cycle operation. The
program command sequence is initiated by
writing two unlock write cycles, followed by the
program set-up command. The program ad-
dress and data are written next, which in turn
initiate the Embedded Program algorithm. The
system is not required to provide further con-
trols or timings. The device automatically pro-
vides internally generated program pulses and
verifies the programmed cell margin.
on page 29
quirements for the byte program command se-
quence. Note that the autoselect, SecSi Sector,
and CFI modes are unavailable while a pro-
gramming operation is in progress.
When the Embedded Program algorithm is
complete, the device then returns to the read
mode and addresses are no longer latched. The
system can determine the status of the pro-
gram operation by using DQ7, DQ6, or RY/BY#.
Refer to
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored.
Note that a hardware reset immediately ter-
minates the program operation. The program
command sequence should be reinitiated once
the device returns to the read mode, to ensure
data integrity.
Programming is allowed in any sequence and
across sector boundaries. A bit cannot be
programmed from “0” back to a “1.” At-
26
“Write Operation Status” on page 30
for further information.
TM
shows the address and data re-
Sector/Exit SecSi Sector
shows the address and
Table 14,
“SecSi
Am29LV320D
TM
tempting to do so may cause the device to set
DQ5 = 1, or cause the DQ7 and DQ6 status bits
to indicate the operation was successful. How-
ever, a succeeding read shows that the data is
still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster
than using the standard program command se-
quence. The unlock bypass command sequence
is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing
the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cy-
cle unlock bypass program command sequence
is all that is required to program in this mode.
The first cycle in this sequence contains the un-
lock bypass program command, A0h; the sec-
ond cycle contains the program address and
data. Additional data is programmed in the
same manner. This mode dispenses with the
initial two unlock cycles required in the stan-
dard program command sequence, resulting in
faster total programming time.
page 29
mand sequence.
During the unlock bypass mode, only the Un-
lock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass
mode, the system must issue the two-cycle un-
lock bypass reset command sequence. The first
cycle must contain the data 90h. The second
cycle need only contain the data 00h. The de-
vice then re turns to the read mode.
The device offers accelerated program opera-
tions through the WP#/ACC pin. When the sys-
tem asserts V
device automatically enters the Unlock Bypass
mode. The system may then write the two-cy-
cle Unlock Bypass prog ram comm and se-
quence. The device uses the higher voltage on
the WP#/ACC pin to accelerate the operation.
Note that the WP#/ACC pin must not be at V
any operation other than accelerated program-
ming, or device damage may result. In addi-
tion, the WP#/ACC pin must not be left floating
or unconnected; inconsistent behavior of the
device may result.
Figure 4, on page 27
for the program operation. Refer to the table
“Erase and Program Operations” on page 41
parameters, and
ing diagrams.
shows the requirements for the com-
H H
Figure 18, on page 42
on the WP#/ACC pin, the
illustrates the algorithm
November 15, 2004
Table 14, on
for tim-
for
HH