AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 13

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Automatic Sleep Mode
The automatic sleep mode minimizes Flash de-
vice energy consumption. The device automati-
cally enables this mode when addresses remain
stable for t
mode is independent of the CE#, WE#, and
OE# control signals. Standard address access
timings provide new data when addresses are
changed. While in sleep mode, output data is
latched and always available to the system. I
in the
represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method
of resetting the device to reading array data.
When the RESET# pin is driven low for at least
a period of t
nates any operation in progress, tristates all
output pins, and ignores all read/write com-
mands for the duration of the RESET# pulse.
The device also resets the internal state ma-
chine to reading array data. The operation that
was interrupted should be reinitiated once the
device is ready to accept another command se-
quence, to ensure data integrity.
Current is reduced for the duration of the RE-
SET# pulse. When RESET# is held at V
V, the device draws CMOS standby current
November 15, 2004
Sector
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
“DC Characteristics” on page 35
Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 1 of 2)
ACC
RP
, the device immediately termi-
Sector Address
+ 30 ns. The automatic sleep
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
A20–A12
(Kbytes/Kwords)
Sector Size
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SS
table
±0.3
Am29LV320D
CC4
(I
V
The RESET# pin may be tied to the system
reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to
read the boot-up firmware from the Flash
memory.
If RESET# is asserted during a program or
erase operation, the RY/BY# pin remains a “0”
(busy) until the internal reset operation is com-
plete, which requires a time of t
Embedded Algorithms). The system can thus
monitor RY/BY# to determine whether the
reset operation is complete. If RESET# is as-
serted when a program or erase operation is
not executing (RY/BY# pin is “1”), the reset op-
eration is completed within a time of t
during Embedded Algorithms). The system can
read data t
V
Refer to the AC Characteristics tables for RE-
SET# parameters and to
for the timing diagram.
Output Disable Mode
When the OE# input is at V
device is disabled. The output pins are placed in
the high impedance state.
0C0000h–0CFFFFh
0D0000h–0DFFFFh
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0E0000h–0EFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
0F0000h–0FFFFFh
Address Range
SS
IH
CC4
.
±0.3 V, the standby current is greater.
). If RESET# is held at V
(x8)
RH
after the RESET# pin returns to
Figure 15, on page 39
020000h–027FFFh
030000h–037FFFh
040000h–047FFFh
050000h–057FFFh
060000h–067FFFh
070000h–077FFFh
080000h–087FFFh
090000h–097FFFh
018000h–01FFFFh
028000h–02FFFFh
038000h–03FFFFh
048000h–04FFFFh
058000h–05FFFFh
068000h–06FFFFh
078000h–07FFFFh
088000h–08FFFFh
000000h–07FFFh
010000h–17FFFh
008000h–0FFFFh
IH
Address Range
, output from the
IL
(x16)
but not within
READY
READY
(during
(not
13