DSPIC33EP512MU810-I/PF Microchip Technology, DSPIC33EP512MU810-I/PF Datasheet - Page 148

• Manufacturer Part Number: DSPIC33EP512MU810-I/PF
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
In addition, DMA transfers can be triggered by Timers
as well as external interrupts. Each DMA channel is
unidirectional. Two DMA channels must be allocated to
read and write to a peripheral. If more than one channel
receive a request to transfer data, a simple fixed priority
scheme, based on channel number, dictates which
channel completes the transfer and which channel, or
channels, are left pending. Each DMA channel moves
a block of data, after which it generates an interrupt to
the CPU to indicate that the block is available for
processing.
The
capabilities:
• Up to 15 DMA channels
• Register Indirect With Post-increment Addressing
• Register Indirect Without Post-increment
TABLE 8-1:
DS70616E-page 148
INT0 – External Interrupt 0
IC1 – Input Capture 1
IC2 – Input Capture 2
IC3 – Input Capture 3
IC4 – Input Capture 4
OC1 – Output Compare 1
OC2 – Output Compare 2
OC3 – Output Compare 3
OC4 – Output Compare 4
TMR2 – Timer2
TMR3 – Timer3
TMR4 – Timer4
TMR5 – Timer5
SPI1 Transfer Done
SPI2 Transfer Done
SPI3 Transfer Done
SPI4 Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
UART3RX – UART3 Receiver
UART3TX – UART3 Transmitter
UART4RX – UART4 Receiver
Peripheral to DMA Association
mode
Addressing mode
DMA
controller
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
provides
these
DMAxREQ Register
IRQSEL<7:0> Bits
00000000
00000001
00000101
00100101
00100110
00000010
00000110
00011001
00011010
00000111
00001000
00011011
00011100
00001010
00100001
01011011
01111011
00001011
00001100
00011110
00011111
01010010
01010011
01011000
functional
Preliminary
• Peripheral Indirect Addressing mode (peripheral
• CPU interrupt after half or full-block transfer com-
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
• DMA request for each channel can be selected
Debug support features
The peripherals that can utilize DMA are listed in
Table
(Values to Read from
generates destination address)
plete
requests) transfer initiation
DPSRAM start addresses after each block trans-
fer complete)
from any supported interrupt source
0x02B6 (U4RXREG)
DMAxPAD Register
0x0226 (U1RXREG)
0x0236 (U2RXREG)
0x0256 (U3RXREG)
0x02A8 (SPI3BUF)
0x02C8 (SPI4BUF)
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x014C (IC2BUF)
0x015C (IC4BUF)
0x0144 (IC1BUF)
0x0154 (IC3BUF)
8-1.
Peripheral)
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 2009-2011 Microchip Technology Inc.
DMAxPAD Register
0x0224 (U1TXREG)
0x0234 (U2TXREG)
0x0254 (U3TXREG)
(Values to Write to
0x02C8 (SPI4BUF)
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x02A8 (SPI3BUF)
0x090E (OC2RS)
0x0904 (OC1RS)
0x0918 (OC3RS)
0x0922 (OC4RS)
0x091A (OC3R)
0x0906 (OC1R)
0x0910 (OC2R)
0x0924 (OC4R)
Peripheral)
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