DSPIC33EP512MU810-I/PF Microchip Technology, DSPIC33EP512MU810-I/PF Datasheet - Page 172

• Manufacturer Part Number: DSPIC33EP512MU810-I/PF
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 9-5:
DS70616E-page 172
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-5
bit 4-3
bit 2-0
Note 1:
ENAPLL
R/W-0
R/W-0
This register resets only on a Power-on Reset (POR).
APLLPOST<2:0>
ENAPLL: Enable Auxiliary PLL (APLL) and Select APLL as USB Clock Source bit
1 = APLL is enabled, the USB clock source is the APLL output
0 = APLL is disabled, the USB clock source is the input clock to the APLL
APLLCK: APLL Phase Locked Status bit
1 = APLL is in lock
0 = APLL is not in lock
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary PLL or oscillator provides the source clock for auxiliary clock divider
0 = Primary PLL provides the source clock for auxiliary clock divider
AOSCMD<1:0>: Auxiliary Oscillator Mode bits
11 = EC (External Clock) mode select
10 = XT (Crystal) Oscillator mode select
01 = HS (High-Speed) Oscillator mode select
00 = Auxiliary Oscillator Disabled (default)
ASRCSEL: Select Reference Clock Source for APLL bit
1 = Primary Oscillator is the clock source for APLL
0 = Auxiliary Oscillator is the clock source for APLL
FRCSEL: Select FRC as Reference Clock Source for APLL bit
1 = FRC is clock source for APLL
0 = Auxiliary oscillator or Primary Oscillator is the clock source for APLL (determined by ASRCSEL bit)
Unimplemented: Read as ‘0’
APLLPOST<2:0>: Select PLL VCO Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256 (default)
Unimplemented: Read as ‘0’
APLLPRE<2:0>: PLL Phase Detector Input Divider bits
111 = Divided by 12
110 = Divided by 10
101 = Divided by 6
100 = Divided by 5
011 = Divided by 4
010 = Divided by 3
001 = Divided by 2
000 = Divided by 1 (default)
APLLCK
R/W-0
R/W-0
ACLKCON3: AUXILIARY CLOCK CONTROL REGISTER 3
W = Writable bit
‘1’ = Bit is set
SELACLK
R/W-0
R/W-0
R/W-0
U-0
Preliminary
—
AOSCMD<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
ASRCSEL
R/W-0
R/W-0
 2009-2011 Microchip Technology Inc.
APLLPRE<2:0>
x = Bit is unknown
(1)
FRCSEL
R/W-0
R/W-0
R/W-0
U-0
—
bit 8
bit 0