KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 22

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

Pin Description for KSZ8841-32 Chip (32-Bit)
October 2007
Micrel, Inc.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
TEST_EN
SCAN_EN
P1LED2
P1LED1
P1LED0
NC
NC
NC
DGND
VDDIO
RDYRTNN
BCLK
DATACSN
PMEN
Type
I
I
Opu
Opu
Opu
Opu
Opu
Opu
Gnd
P
Ipd
Ipd
Ipu
Opu
Pin Function
Test Enable
For normal operation, pull-down this pin-to-ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this pin-to-ground.
Port 1 LED indicators
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27.
No Connect.
No Connect.
No Connect.
Digital ground
3.3V digital V
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the
host doesn’t connect to this pin, assert this pin.
For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
DATA Chip Select Not (For KSZ8841-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
When DATACSN is Low, the data path can be accessed regardless of the value of AEN,
A15-A1, and the content of the BANK select register.
Power Management Event Not
When asserted (Low), this signal indicates that a power management event has occurred
in the system when a wake-up signal is detected by KSZ8841M.
P1LED3
P1LED2
P1LED1
P1LED0
P1LED3
P1LED2
P1LED1
P1LED0
2
2
DDIO
input power supply for IO with well decoupling capacitors.
1
defined as follows:
22
Chip Global Control Register: CGCR
bit [15,9]
[0,0] Default
—
Link/Act
Full duplex/Col
Speed
Reg. CGCR bit [15,9]
[1,0]
Act
Link
Full duplex/Col
Speed
[0,1]
—
100Link/Act
10Link/Act
Full duplex
[1,1]
—
—
—
—
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6