KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 63

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

Bank 16 Transmit Control Register (0x00): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bank 16 Transmit Status Register (0x02): TXSR
This register keeps the status of the last transmitted frame.
October 2007
Micrel, Inc.
Bit
15
14-13
12-4
3
2
1
0
Bit
15
14
13
12
11-6
5-0
-
0x0
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
-
Default Value
Default Value
R/W
RO
RW
RO
RW
RW
RW
RW
R/W
RO
RO
RO
RO
RO
RO
Description
Reserved.
Reserved.
Reserved.
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled. The
KSZ8841M transmits a PAUSE frame when the Receive Buffer capacity reaches a threshold
level that will cause the buffer to overflow.
When this bit is set and the KSZ8841M is in half-duplex mode, back-pressure flow control is
enabled. When this bit is cleared, no transmit flow control is enabled.
TXPE Transmit Padding Enable
When this bit is set, the KSZ8841M automatically adds a padding field to a packet shorter than
64 bytes.
Note: Setting this bit requires enabling the add CRC feature to avoid CRC errors for the
transmit packet.
TXCE Transmit CRC Enable
When this bit is set, the KSZ8841M automatically adds a CRC checksum field to the end of a
transmit frame.
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When reset,
the transmit process is placed in the stopped state after the transmission of the current frame
is completed.
Description
Reserved.
TXUR Transmit Underrun
This bit is set when underrun occurs.
Note: This is a fatal status. Software should guarantee that no underrun condition occurred
when enabling the early transmit function. The system or the QMU requires a reset or restart
to recover from an underrun condition.
To aviod transmit underun condition, the user has to make sure that the host interface speed
(bandwidth) is faster than the ethernet port.
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
Reserved.
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this register
belongs to the frame with this ID.
63
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6