KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 65

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

Bank 16 RXQ Memory Information Register (0x0A): RXMIR
This register indicates the amount of receive data available in the RXQ of the QMU module.
Bank 17 TXQ Command Register (0x00): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
Bank 17 RXQ Command Register (0x02): RXQCR
This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ
frame buffer is read only by the host and the memory space is released.
October 2007
Micrel, Inc.
Bit
15-13
12-0
Bit
15-1
0
Bit
15-1
0
-
-
-
0x0
-
0x0
Default Value
Default Value
Default Value
R/W
RO
RO
R/W
RO
RW
R/W
RO
RW
Description
Reserved.
RXMA Receive Packet Data Available
The amount of Receive packet data available is represented in units of byte. The RXQ
memory is used for both frame payload, status word. There is total 4096 bytes in RXQ. This
counter will update after a complete packet is received and also issues an interrupt when
receive interrupt enable IER[13] in Bank 18 is set.
Note: Software must be written to empty the RXQ memory to allow for the new RX frame. If
this is not done, the frame may be discarded as a result of insufficient RXQ memory.
Description
Reserved
TXETF Enqueue TX Frame
When this bit is written as 1, the current TX frame prepared in the TX buffer is queued for
transmit.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait
for the bit to be cleared before setting up another new TX frame.
Description
Reserved.
RXRRF Release RX Frame
When this bit is written as 1, the current RX frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should wait for
the bit to be cleared before processing new RX frame.
65
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6