KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 86

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

Additional MIB Information
October 2007
Micrel, Inc.
Offset
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Example:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all
the counters at least every 30 seconds.
MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
Counter Name
TxMulticastPkts
TxUnicastPkts
TxDeferred
TxTotalCollision
TxExcessiveCollision
TxSingleCollision
TxMultipleCollision
Then
Write to reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation)
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
Read reg. IADR4 (MIB counter value 15-0)
Table 12. Port 1 MIB Counters Indirect Memory Offsets
Description
Tx good multicast packets (not including error multicast packets or valid broadcast packets)
Tx good unicast packets
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
Tx total collision, half duplex only
A count of frames for which Tx fails due to excessive collisions
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
// If bit 30 = 0, restart (re-read) from this register
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KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6