KSZ8851-16MLL Micrel Inc, KSZ8851-16MLL Datasheet - Page 55

• Manufacturer Part Number: KSZ8851-16MLL
• Description: Single Ethernet Port + Generic (16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLL

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-3292 - BOARD EVALUATION KSZ8851-16MLL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3252

Interrupt Status Register (0x92 – 0x93): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear.
August 2009
Micrel, Inc.
Bit
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
15
14
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default Value
Default Value
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
R/W
RO
(W1C)
RO
(W1C)
Description
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
Reserved
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
Reserved
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
Reserved
TXSAIE Transmit Space Available Interrupt Enable
When this bit is set, the Transmit memory space available interrupt is enabled.
When this bit is reset, the Transmit memory space available interrupt is disabled.
RXWFDIE Receive Wake-up Frame Detect Interrupt Enable
When this bit is set, the Receive wakeup frame detect interrupt is enabled.
When this bit is reset, the Receive wakeup frame detect interrupt is disabled.
RXMPDIE Receive Magic Packet Detect Interrupt Enable
When this bit is set, the Receive magic packet detect interrupt is enabled.
When this bit is reset, the Receive magic packet detect interrupt is disabled.
LDIE Linkup Detect Interrupt Enable
When this bit is set, the wake-up from linkup detect interrupt is enabled.
When this bit is reset, the linkup detect interrupt is disabled.
EDIE Energy Detect Interrupt Enable
When this bit is set, the wake-up from energy detect interrupt is enabled.
When this bit is reset, the energy detect interrupt is disabled.
Reserved.
DEDIE Delay Energy Detect Interrupt Enable
When this bit is set, the delay energy detect interrupt is enabled.
When this bit is reset, the delay energy detect interrupt is disabled.
Note: the delay energy detect interrupt till device is ready for host access.
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link down,
or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit Interrupt Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the
55
KSZ8851-16MLL/MLLI
M9999-083109-2.0