DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 187

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

27.1 BERT Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire
synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the registers
BBC1/BBC2/BBC3/BBC4 and BEC1/BEC2/BEC3 and clears the internal count. This bit should be toggled from low to high
whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a subsequent loads.
Bits 2 to 4/Pattern Select Bits (PS0 to PS2)
Bit 5/Receive Invert Data Enable (RINV).
Bit 6/Transmit Invert Data Enable (TINV).
Bit 7/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be
generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set
again for a subsequent loads.
PS2
0
0
0
0
1
1
1
1
0 = do not invert the incoming data stream
1 = invert the incoming data stream
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
PS1
0
0
1
1
0
0
1
1
TC
7
0
PS0
0
1
0
1
0
1
0
1
Pseudorandom 2E7–1
Pseudorandom 2E11–1
Pseudorandom 2E15–1
Pseudorandom Pattern QRSS. A 2
zero restriction.
Repetitive Pattern
Alternating Word Pattern
Modified 55 Octet (Daly) Pattern The Daly pattern is a repeating 55
octet pattern that is byte-aligned into the active DS0 time slots. The
pattern is defined in an ATIS (Alliance for Telecommunications
Industry Solutions) Committee T1 Technical Report Number 25
(November 1993).
Pseudorandom 2E9 - 1
TINV
BC1
BERT Control Register 1
E0h
6
0
RINV
5
0
PATTERN DEFINITION
PS2
4
0
187 of 270
20
- 1 pattern with 14 consecutive
PS1
3
0
PS0
2
0
LC
1
0
RESYNC
0
0