DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 52

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

9. CLOCK MAP
Figure 9-1
clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only
one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification
and clarity.
Figure 9-1. Clock Map
The TCLK MUX is dependent on the state of the TCSS0 and TCSS1 bits in the LIC1 register and the
state of the TCLK pin.
TCSS1
RXCLK
TXCLK
TO
LIU
0
0
1
1
RCL = 1
RCL = 0
TCSS0
shows the clock map of the DS21455/DS21458. The routing for the transmit and receive
2.048 TO 1.544
SYNTHESIZER
PRE-SCALER
0
1
0
1
MCLK
LOCAL
LOOPBACK
LLB = 0
LLB = 1
The TCLK pin (C) is always the source of Transmit Clock.
Switch to the recovered clock (B) when the signal at the TCLK pin fails to
transition after 1 channel time.
Use the scaled signal (A) derived from MCLK as the Transmit Clock. The TCLK
pin is ignored.
Use the recovered clock (B) as the Transmit Clock. The TCLK pin is ignored.
LIC4.MPS0
LIC4.MPS1
LIC2.3
JITTER ATTENUATOR
SEE LIC1 REGISTER
JAS = 0
OR
DJA = 1
JAS = 1
AND
DJA = 0
LTCA
LTCA
JAS = 0
AND
DJA = 0
JAS = 1
OR
DJA = 1
REMOTE
LOOPBACK
RLB = 1
RLB = 0
TRANSMIT CLOCK SOURCE
52 of 270
DJA = 1
DJA = 0
FRAMER
LOOPBACK
FLB = 0
FLB = 1
TRANSMIT
FORMATTER
RECEIVE
FRAMER
8 x PLL
PAYLOAD
LOOPBACK
(SEE NOTES)
PLB = 1
PLB = 0
A
B
BPCLK
SYNTH
C
TCLK
MUX
8XCLK
BPCLK
RCLK
TCLK