DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 95

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DS21455

Manufacturer Part Number
DS21455
Description
Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
Manufacturer
Maxim Integrated Products
Datasheets

Specifications of DS21455

Product
Framer
Number Of Transceivers
4
Data Rate
64 Kbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
328 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
BGA

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DS21455/DS21458 Quad T1/E1/J1 Transceivers
17.1.2.2 Force Receive Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling-bit positions to a one.
This is done by using the per-channel register, which is described in the Special Per-Channel Operation
section. The user sets the BTCS bit in the PCPR register. The channels that are to be forced to one are
selected by writing to the PCDR1–PCDR3 registers.
17.1.2.3 Receive-Signaling Freeze
The signaling data in the four-multiframe signaling buffer will be frozen in a known good state upon
either a loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the
requirements of BellCore TR–TSY–000170 for signaling freezing. To allow this freeze action to occur,
the RFE control bit (SIGCR.4) should be set high. The user can force a freeze by setting the RFF control
bit (SIGCR.3) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The
four multiframe buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin
(and at the RSER pin if receive signaling reinsertion is enabled). When freezing is enabled (RFE = 1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.
When the error condition subsides, the signaling data will be held in the old state for at least an additional
9ms (or 4.5ms in D4 framing mode) before being allowed to be updated with new signaling data.
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