DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 56

• Manufacturer Part Number: DS3112N+W
• Description: Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
• Manufacturer: Maxim Integrated Products

Specifications of DS3112N+W

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-1. T3 Alarm Criteria
Note 1: RAI can also be indicated via FEAC codes in the C-Bit Parity Mode
Note 2: LOS is not defined for unipolar (binary) operation.
CONDITION
Idle Signal
ALARM/
(Note 1)
LOS
LOF
RAI
AIS
Alarm Indication Signal
Properly framed 1010...
pattern, which is aligned
with the 1 just after each
overhead bit and all C bits
are set to zero
Loss Of Signal
(Note 2)
Loss Of Frame
Too many F bits or M bits in
error
Remote Alarm Indication
(This is also referred to as
SEF/AIS in Bellcore GR-
820)
Inactive: X1 = X2 = 1
Active: X1 = X2 = 0
Properly framed 1100...
pattern, which is aligned
with the 11 just after each
overhead bit and the C bits
in Subframe 3 are zero.
DEFINITION
In each 84-bit information
field, the properly aligned
10... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and all C bits
are majority decoded to be
zero during this time
192 consecutive zeros
Three or more F bits in error
out of 16 consecutive, or 2 or
more M bits in error out of
four consecutive
X1 and X2 = 0 for four
consecutive M frames (426µs)
In each 84-bit information
field, the properly aligned
1100... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and the C bits
in Subframe 3 are majority
decoded to be zero during this
time.
56 of 133
SET CRITERIA
In each 84 bit information
field, the properly aligned
10... pattern is detected with
4 or more bit errors (out of 84
possible) for 1024
consecutive information bit
fields (1.95ms)
No EXZ events over a 192-
bit window that starts with
the first one received
Synchronization occurs
X1 and X2 = 1 for four
consecutive M frames
(426µs)
In each 84-bit information
field, the properly aligned
1100... pattern is detected
with four or more bit errors
(out of 84 possible) for 1024
consecutive information bit
fields (1.95ms)
CLEAR CRITERIA
DS3112