DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 63

• Manufacturer Part Number: DS3112N+W
• Description: Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
• Manufacturer: Maxim Integrated Products

Specifications of DS3112N+W

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 6: T2/E2/G.747 Transmit Loss Of Frame Generation (LOFGn where n = 1 to 7). A zero to one
transition on this bit will cause the T2/E2/G.747 transmit formatter to generate enough framing bit errors to cause
the far end to lose frame synchronization. This bit must be cleared and set again for a subsequent set of errors to be
generated
Bits 8 to 11: E2 Transmit National Bit Setting (E2Snn where n = 1 to 4). These bits are ignored in the T3 and
G.747 modes. The received Sn can be read from the T2E2 Status Register 2.
G.747 Mode
T3 Mode
E3 Mode
MODE
0 = force the Sn bit to zero
1 = force the Sn bit to one
.
—
—
15
—
—
Four consecutive F bit errors
Four consecutive FAS words of 0000101111 generated instead of the normal FAS word,
which is 1111010000 (i.e., all FAS bits are inverted)
Four consecutive FAS words of 000101111 generated instead of the normal FAS word,
which is 111010000 (i.e., all FAS bits are inverted)
7
LOFG7
14
—
—
6
0
T2E2CR2
T2/E2 Control Register 2
32h
LOFG6
13
—
—
5
0
FRAMING ERRORS GENERATED
LOFG5
63 of 133
12
—
—
4
0
LOFG4
E2Sn4
11
—
3
0
LOFG3
E2Sn3
10
—
2
0
LOFG2
E2Sn2
—
1
9
0
LOFG1
E2Sn1
—
DS3112
0
0
8