DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 80

• Manufacturer Part Number: DS3112N+W
• Description: Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
• Manufacturer: Maxim Integrated Products

Specifications of DS3112N+W

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Force Resynchronization (RESYNC). A low to high transition will force the receive BERT synchronizer
to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host
wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent
resynchronization.
Bit 1: Load Bit and Error Counters (LC). A low to high transition latches the current bit and error counts into
the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a
subsequent loads.
Bits 2 to 4: Pattern Select Bits 0 (PS0 to PS2).
Bit 5: Receive Invert Data Enable (RINV).
Bit 6: Transmit Invert Data Enable (TINV).
Bit 7: Pattern Bank Select (PBS)
If PBS = 0:
000 = Pseudorandom Pattern 2
001 = Pseudorandom Pattern 2
010 = Pseudorandom Pattern 2
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = Illegal State
111 = Illegal State
If PBS = 1:
000 = Psuedorandom Pattern 2
001 = Pseudorandom Pattern 2
010 = Pseudorandom Pattern 2
011 = Illegal State
10X = Illegal State (X = 0 or 1)
11X = lllegal State (X = 0 or 1)
0 = do not invert the incoming data stream
1 = invert the incoming data stream
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
0 = PS[2:0] select a pattern from Pattern Bank 0
1 = PS[2:0] select a pattern from Pattern Bank 1
IESYNC
PBS
15
7
0
0
IEBED
TINV
14
6
0
0
BERTC0
BERT Control Register 0
70h
7
11
15
9
20
23
- 1 (ANSI T1.403-1999 Annex B)
- 1
RINV
- 1 (ITU O.153)
- 1 (ITU O.151)
- 1 (non-QRSS)
- 1 (ITU O.151)
IEOF
13
5
0
0
80 of 133
PS2
n/a
12
4
0
-
RPL3
PS1
11
3
0
0
RPL2
PS0
10
2
0
0
RPL1
LC
1
0
9
0
RESYNC
RPL0
DS3112
0
0
8
0