DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 93

• Manufacturer Part Number: DS3112N+W
• Description: Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
• Manufacturer: Maxim Integrated Products

Specifications of DS3112N+W

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3112
(i.e., the FIFO has been read from and then allowed to fill up again). The setting of this bit can cause a hardware
interrupt to occur if the ROVR bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit
in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is
read.
Bit 14: Receive FIFO Empty (REMPTY). This real-time bit will be set to a one when the Receive FIFO is empty
and will be set to a zero when the Receive FIFO is not empty.
Bit 15: Receive Abort Sequence Detected (RABT). This latched read-only event-status bit will be set to a one
each time the receive HDLC controller detects seven or more ones in a row during packet reception. If the receive
HDLC is not currently receiving a packet, then seven or more ones in a row will not trigger this status bit. This bit
will be cleared when read and will not be set again until another abort is detected (at least one valid flag must be
detected before another abort can be detected). The setting of this bit can cause a hardware interrupt to occur if the
RABT bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
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