LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 217

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
0C42h-0C50h
0C24
REGISTER #
0C1Ah
0C1Bh
0C1Ch
0C1Dh
0C1Eh
0C1Fh
0C10h
0C11h
0C12h
0C13h
0C14h
0C15h
0C16h
0C17h
0C18h
0C19h
0C20h
0C21h
0C22h
0C23h
0C40h
0C41h
h
-0C3F
Table 13.14 Indirectly Accessible Switch Control and Status Registers (continued)
h
MAC_RX_128_TO_255_CNT_2
MAC_RX_CRCERR_CNT_2
MAC_RX_UNDSZE_CNT_2
MAC_RX_256_TO_511_CNT_2
MAC_RX_OVRSZE_CNT_2
MAC_RX_MULCST_CNT_2
MAC_RX_BRDCST_CNT_2
MAC_TX_FC_SETTINGS_2
MAC_RX_CTLFRM_CNT_2
MAC_RX_512_TO_1023_CNT_2
MAC_RX_PKTLEN_CNT_2
MAC_RX_65_TO_127_CNT_2
MAC_RX_1024_TO_MAX_CNT_2
MAC_RX_GOODPKTLEN_CNT_2
MAC_RX_PKTOK_CNT_2
MAC_RX_PAUSE_CNT_2
MAC_RX_SYMBL_CNT_2
MAC_RX_ALIGN_CNT_2
MAC_RX_FRAG_CNT_2
MAC_RX_JABB_CNT_2
MAC_RX_64_CNT_2
MAC_TX_CFG_2
RESERVED
RESERVED
SYMBOL
DATASHEET
Port 2 MAC Receive Undersize Count Register,
Section 13.4.2.3
Port 2 MAC Receive 64 Byte Count Register,
Port 2 MAC Receive 65 to 127 Byte Count Register,
Section 13.4.2.5
Port 2 MAC Receive 128 to 255 Byte Count Register,
Section 13.4.2.6
Port 2 MAC Receive 256 to 511 Byte Count Register,
Section 13.4.2.7
Port 2 MAC Receive 512 to 1023 Byte Count Register,
Section 13.4.2.8
Port 2 MAC Receive 1024 to Max Byte Count Register,
Section 13.4.2.9
Port 2 MAC Receive Oversize Count Register,
Section 13.4.2.10
Port 2 MAC Receive OK Count Register,
Port 2 MAC Receive CRC Error Count Register,
Section 13.4.2.12
Port 2 MAC Receive Multicast Count Register,
Section 13.4.2.13
Port 2 MAC Receive Broadcast Count Register,
Section 13.4.2.14
Port 2 MAC Receive Pause Frame Count Register,
Section 13.4.2.15
Port 2 MAC Receive Fragment Error Count Register,
Section 13.4.2.16
Port 2 MAC Receive Jabber Error Count Register,
Section 13.4.2.17
Port 2 MAC Receive Alignment Error Count Register,
Section 13.4.2.18
Port 2 MAC Receive Packet Length Count Register,
Section 13.4.2.19
Port 2 MAC Receive Good Packet Length Count Register,
Section 13.4.2.20
Port 2 MAC Receive Symbol Error Count Register,
Section 13.4.2.21
Port 2 MAC Receive Control Frame Count Register,
Section 13.4.2.22
Reserved for Future Use
Port 2 MAC Transmit Configuration Register,
Port 2 MAC Transmit Flow Control Settings Register,
Section 13.4.2.24
Reserved for Future Use
217
REGISTER NAME
Section 13.4.2.11
Revision 1.4 (07-07-10)
Section 13.4.2.23
Section 13.4.2.4