LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 49

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
STRAP NAME
manual_FC_strap_1
auto_mdix_strap_2
manual_mdix_strap_2
autoneg_strap_2
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
Port 1 Manual Flow Control Enable Strap: Configures the
default value of the
Select (MANUAL_FC_1)
Control Register
This strap affects the default value of the following register
bits (x=1):
Port 2 Auto-MDIX Enable Strap: Configures the default
value of the
Hardware Configuration Register
This strap is used in conjunction with
to configure Port 2 Auto-MDIX functionality when the
MDIX Control (AMDIXCTRL)
Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
strap settings should be used for auto-MDIX configuration.
Refer to the respective register definition sections for
additional information.
Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1)
for Port 2 when the auto_mdix_strap_2 is low and the
MDIX Control (AMDIXCTRL)
Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
strap settings are to be used for auto-MDIX configuration.
Port 2 Auto Negotiation Enable Strap: Configures the
default value of the
in the (x=2)
(PHY_BASIC_CONTROL_x).
This strap may also affect the default value of the following
register bits (x=2):
Refer to the respective register definition sections for
additional information.
Asymmetric Pause
x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
Speed Select LSB (PHY_SPEED_SEL_LSB)
Mode (PHY_DUPLEX)
Control Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex
the
(PHY_AN_ADV_x)
PHY Mode (MODE[2:0])
Modes Register (PHY_SPECIAL_MODES_x)
Port x PHY Auto-Negotiation Advertisement Register
Port x PHY Basic Control Register
AMDIX_EN Strap State Port 2
DATASHEET
(MANUAL_FC_1).
Port 1 Full-Duplex Manual Flow Control
Auto-Negotiation (PHY_AN)
and
49
and
bit in the
bits of the
Symmetric Pause
bits of the
10BASE-T Half Duplex
bit in the (x=2)
bit of the (x=2)
(HW_CFG).
Port 1 Manual Flow
Port x PHY Basic
manual_mdix_strap_2
Port x PHY Special
bits of the
bit of the
indicates the
indicates the
Port x PHY
Port x PHY
and
enable bit
Duplex
bits of
Auto-
Auto-
Port
PIN / DEFAULT
VALUE
0b
AMDIX2 LED1P
0b
1b
Revision 1.4 (07-07-10)
Note 4.1