LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 227
LAN9303I-ABZJ
Manufacturer Part Number
LAN9303I-ABZJ
Description
Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
Manufacturer
SMSC
Datasheet
1.LAN9303-ABZJ.pdf
(367 pages)
Specifications of LAN9303I-ABZJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.4.2
13.4.2.1
31:12
BITS
11:8
7:4
3:0
RESERVED
Device Type Code (DEVICE_TYPE)
Chip Version Code (CHIP_VERSION)
Revision Code (REVISION)
Switch Port 0, Port 1, and Port 2 CSRs
This section details the switch Port 0, Port 1, and Port 2 CSRs. Each port provides a functionally
identical set of registers which allow for the configuration of port settings, interrupts, and the monitoring
of the various packet counters.
Because the Port 0, Port 1, and Port 2 CSRs are functionally identical, their register descriptions have
been consolidated. A lowercase “x” has been appended to the end of each switch port register name
in this section, where “x” should be replaced with “0”, “1”, or “2” for the Port 0, Port 1, or Port 2 registers
respectively. A list of the Switch Port 0, Port 1, and Port 2 registers and their corresponding register
numbers is included in
Port x MAC Version ID Register (MAC_VER_ID_x)
This read-only register contains switch device ID information, including the device type, chip version
and revision codes.
Register #:
Table
Port0: 0400h
Port1: 0800h
Port2: 0C00h
DESCRIPTION
13.14.
DATASHEET
227
Size:
32 bits
TYPE
RO
RO
RO
RO
Revision 1.4 (07-07-10)
DEFAULT
5h
8h
3h
-
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