TDA9109 STMicroelectronics, TDA9109 Datasheet - Page 16

• Manufacturer Part Number: TDA9109
• Description: Multimedia Misc DISC BY STM 11/99
• Manufacturer: STMicroelectronics
• Type: Low Cost Deflection Processorr

Specifications of TDA9109

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Package / Case: SPDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDA9109/S
OPERATING DESCRIPTION
I - GENERAL CONSIDERATIONS
I.1 - Power Supply
The typical values of the power supply voltages
V
mum operation is obtained for V
and 13.2V and V
In order to avoid erratic operation of the circuit during
the transient phase of V
off, the value of V
is less than 7.5V typ. or if V
the outputs of the circuit are inhibited.
Similarly, before V
are reset to their default value.
In order to have very good power supply rejection,
the circuit is internally supplied by several voltage
references (typ. value : 8V). Two of these voltage
references are externally accessible, one for the
vertical and one for the horizontal part. They can be
used to bias external circuitry (if I
5mA). It is necessary to filter the voltage references
by external capacitors connected to ground, in order
to minimize the noise and consequently the "jitter"
on vertical and horizontal output signals.
I.2 - I
TDA9109/S belongs to the I
family. Instead of being controlled by DC voltages
on dedicated control pins, each adjustment can be
done via the I
The I
input. The general function and the bus protocol are
specified in the Philips-bus data sheets.
The interface (Data and Clock) is a comparator with
hysteresis ; the thresholds (less then 2.2V on rising
edge, more than 0.8V on falling edge with 5V
supply) are TTL-compatible. Spikes of up to 50ns
are filtered by an integrator and the maximum clock
speed is limited to 400kHz.
The data line (SDA) can be used bidirectionally.
In read-mode the IC sends reply information
(1 byte) to the micro-processor.
The bus protocol prescribes a full-byte transmis-
sion in all cases. The first byte after the start
condition is used to transmit the IC-address
(hexa 8C for write, 8D for read).
16/30
CC
and V
2
2
C Control
C bus is a serial bus with a clock and a data
DD
2
are 12V and 5V respectively. Opti-
C Interface.
DD
CC
DD
between 4.5 and 5.5V.
and V
reaches 4V, all the I
CC
DD
and V
DD
are monitored : if V
2
is less than 4.0V typ.,
C controlled device
DD
CC
LOAD
switching on, or
between 10.8
is less than
2
C register
CC
I.3 - Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controls to affect) and the third byte the correspond-
ing data byte. It is possible to send more than one
data byte to the IC. If after the third byte no stop or
start condition is detected, the circuit increments
automatically by one the momentary subaddress in
the subaddress counter (auto-increment mode).
So it is possible to transmit immediately the follow-
ing data bytes without sending the IC address or
subaddress. This can be useful to reinitialize all the
controls very quickly (flash manner). This proce-
dure can be finished by a stop condition.
The circuit has 16 adjustment capabilities : 3 for the
horizontal part, 4 for the vertical, 2 for the E/W
correction, 2 for the dynamic horizontal phase con-
trol,1 for the Moiré option, 3 for the horizontal and
the vertical dynamic focus and 1 for the B+ refer-
ence adjustment.
17 bits are also dedicated to several controls
(ON/OFF, Horizontal Forced Frequency, Sync Pri-
ority, Detection Refresh and XRAY reset).
I.4 - Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the horizontal and vertical
lock/unlock status, the XRAY activation status and,
the horizontal and vertical polarity detection. It also
contains the sync detection status which is used by
the MCU to assign the sync priority.
A stop condition always stops all the activities of the
bus decoder and switches to high impedance both
the data and clock line (SDA and SCL).
See I
I.5 - Sync Processor
The internal sync processor allows the TDA9109/S
to accept :
- separated horizontal & vertical TTL-compatible
- composite horizontal & vertical TTL-compatible
sync signal,
sync signal.
2
C subaddress and control tables.