MT48LC2M32B2TG-7 IT:G Micron Technology Inc, MT48LC2M32B2TG-7 IT:G Datasheet - Page 21
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MT48LC2M32B2TG-7 IT:G
Manufacturer Part Number
MT48LC2M32B2TG-7 IT:G
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-7_ITG.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7 IT:G
Density
64 Mb
Maximum Clock Rate
143 MHz
Package
86TSOP-II
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
Figure 8:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
READ Command
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x equals CL - 1. This is shown in Figure 10 on page 23 for CL = 1,
CL = 2, and CL = 3; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architecture. A READ command can be
initiated on any clock cycle following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as shown in Figure 11 on page 24, or
each subsequent READ may be performed to a different bank.
A8, A9
A0–A7
BA0, 1
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
HIGH
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
ADDRESS
COLUMN
BANK
21
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands