M25P20-VMN6PB NUMONYX, M25P20-VMN6PB Datasheet - Page 30

• Manufacturer Part Number: M25P20-VMN6PB
• Description: Flash Mem Serial-SPI 3.3V 2M-Bit 256K x 8 8ns 8-Pin SO N Tray
• Manufacturer: NUMONYX

Specifications of M25P20-VMN6PB

• Package: 8SO N
• Cell Type: NOR
• Density: 2 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 4
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI

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Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, subsequently reducing the standby current (from I
as specified in
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction and
the Read Identification (RDID) instruction also allow the Electronic Signature of the device
to be output on Serial Data Output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t
to I
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) Instruction Sequence
S
C
D
CC2
and the Deep Power-down mode is entered.
Table
0
13).
1
2
Instruction
3
4
5
6
Figure
7
17.
DP
Stand-by Mode
t
DP
before the supply current is reduced
Deep Power-down Mode
CC1
to I
AI03753D
CC2
,