XC3S50-4TQG144C Xilinx Inc, XC3S50-4TQG144C Datasheet - Page 30
![FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S50-4TQG144C
Manufacturer Part Number
XC3S50-4TQG144C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S50-4TQG144C
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
97
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX43
Quantity:
240
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan-3 FPGA Family: Functional Description
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that
accept two 18-bit words as inputs to produce a 36-bit prod-
uct. This section provides an introduction to multipliers. For
further details, refer to the “Using Embedded Multipliers”
chapter in UG331.
The input buses to the multiplier accept data in two’s-com-
plement form (either 18-bit signed or 17-bit unsigned). One
such multiplier is matched to each block RAM on the die.
The close physical proximity of the two ensures efficient
30
54
A[17:0]
B[17:0]
Figure 15: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
(a) Asynchronous 18-bit Multiplier
ADDR
CLK
WE
DO
EN
DI
DISABLED
MULT18X18
0000
Figure 16: Embedded Multiplier Primitives
XXXX
aa
READ
P[35:0]
MEM(aa)
www.xilinx.com
1111
bb
MEM(bb)=1111
WRITE
data handling. Cascading multipliers permits multiplicands
more than three in number as well as wider than 18-bits.
The multiplier is placed in a design using one of two primi-
tives: an asynchronous version called MULT18X18 and a
version with a register called MULT18X18S, as shown in
Figure 16a
these primitives are defined in
The CORE Generator system produces multipliers based
on these primitives that can be configured to suit a wide
range of requirements.
A[17:0]
B[17:0]
RST
CLK
(b) 18-bit Multiplier with Register
CE
2222
cc
MEM(cc)=2222
WRITE
and
Figure
MULT18X18S
16b, respectively. The signals for
dd
DS099-2_16_030403
XXXX
READ
DS099-2 (v2.5) December 4, 2009
MEM(dd)
Table
P[35:0]
DS099-2_17_052705
14.
Product Specification
R