XC3S50-4TQG144C Xilinx Inc, XC3S50-4TQG144C Datasheet - Page 83
![FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S50-4TQG144C
Manufacturer Part Number
XC3S50-4TQG144C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S50-4TQG144C
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
97
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX43
Quantity:
240
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 51: CLB Distributed RAM Switching Characteristics
Table 52: CLB Shift Register Switching Characteristics
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
T
DH,
WPH
WPH
Symbol
Symbol
T
T
T
T
SHCKO
SRLDS
SRLDH
T
T
T
T
REG
AH,
WS
AS
DS
, T
, T
WPL
WPL
T
R
WH
Time from the active edge at the CLK input to data
appearing on the distributed RAM output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
Setup time of the F/G address inputs before the active
transition at the CLK input of the distributed RAM
Setup time of the write enable input before the active
transition at the CLK input of the distributed RAM
Hold time of the BX, BY data inputs, the F/G address
inputs, or the write enable input after the active transition
at the CLK input of the distributed RAM
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data
appearing on the shift register output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold time of the BX or BY data input after the active
transition at the CLK input of the shift register
Minimum High or Low pulse width at CLK input
Description
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
0.46
0.46
0.33
0.85
0.46
0.85
Min
Min
0
0
-
-
-5
-5
Max
1.87
Max
3.30
-
-
-
-
-
-
-
-
0.52
0.53
0.37
0.97
0.52
0.97
Min
Min
0
0
-
-
-4
-4
Max
2.15
Max
3.79
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83