XC3S50-4TQG144C Xilinx Inc, XC3S50-4TQG144C Datasheet - Page 94
![FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S50-4TQG144C
Manufacturer Part Number
XC3S50-4TQG144C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S50-4TQG144C
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
97
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX43
Quantity:
240
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 66: Timing for the Master and Slave Parallel Configuration Modes
94
INIT_B
CS_B
RDWR_B
CCLK
D0 - D7
BUSY
PROG_B
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
(Input)
(Open-Drain)
(Input)
(Input)
(Input/Output)
(Inputs)
(Output)
SMCKBY
SMDCC
SMCSCC
SMCCW
Symbol
Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration.
(2)
The time from the rising transition on the CCLK pin to a signal
transition at the BUSY pin
The time from the setup of data at the D0-D7 pins to the rising
transition at the CCLK pin
The time from the setup of a logic level at the CS_B pin to the rising
transition at the CCLK pin
The time from the setup of a logic level at the RDWR_B pin to the
rising transition at the CCLK pin
Figure 36: Waveforms for Master and Slave Parallel Configuration
High-Z
T
SMCCW
T
SMDCC
Description
Byte 0
T
SMCSCC
www.xilinx.com
T
SMCCD
Byte 1
T
SMCKBY
T
Master
CCH
Slave/
Slave
Both
BUSY
1/F
DS099-3 (v2.5) December 4, 2009
Byte n
CCPAR
All Speed Grades
T
SMCKBY
10.0
10.0
10.0
Min
-
T
T
CCL
Product Specification
SMCCCS
Byte n+1
Max
12.0
-
-
-
DS099-3_05_041103
T
SMWCC
Units
High-Z
ns
ns
ns
ns
R