XC3S50-4TQG144C Xilinx Inc, XC3S50-4TQG144C Datasheet - Page 85
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XC3S50-4TQG144C
Manufacturer Part Number
XC3S50-4TQG144C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S50-4TQG144C
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
97
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX43
Quantity:
240
Part Number:
XC3S50-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 55: Block RAM Timing
Clock Distribution Switching Characteristics
Table 56: Clock Distribution Switching Characteristics
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0- and
I1-inputs. Same as BUFGCE enable CE-input
BCKO
BDCK
BCKD
BPWH
BPWL
The numbers in this table are based on the operating conditions set forth in
For minimums, use the values reported by the Xilinx timing analyzer.
For minimums, use the values reported by the Xilinx timing analyzer.
Symbol
R
When reading from the Block
RAM, the time from the active
transition at the CLK input to
data appearing at the DOUT
output
Time from the setup of data at
the DIN inputs to the active
transition at the CLK input of the
Block RAM
Time from the active transition
at the Block RAM’s CLK input to
the point where data is last held
at the DIN inputs
Block RAM CLK signal High
pulse width
Block RAM CLK signal Low
pulse width
Description
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
0.43
1.19
1.19
Min
0
-
-5
Max
2.09
Table
∞
∞
-
-
Speed Grade
31.
Symbol
T
T
GIO
GSI
0.49
1.37
1.37
Min
0
-
0.36
0.53
-4
Speed Grade
-5
Maximum
Max
2.40
∞
∞
-
-
0.41
0.60
-4
Units
ns
ns
ns
ns
ns
Units
ns
ns
85