LFEC10E-3FN256C LATTICE SEMICONDUCTOR, LFEC10E-3FN256C Datasheet - Page 18

• Manufacturer Part Number: LFEC10E-3FN256C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3FN256C

• Package: 256FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 195
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-18 compares the serial and the
parallel implementations.
Figure 2-18. Comparison of General DSP and LatticeECP-DSP Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but
not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.
The resources in each sysDSP block can be configured to support the following four elements:
The number of elements available in each block depends on the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-1 shows the capabilities of the block.
• MULT
• MAC
• MULTADD
• MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)
Accumulator
Multiplier
Single
Function implemented in
Operand
General purpose DSP
A
Σ
x
Operand
B
(Multiply)
(Multiply, Accumulate)
(Multiply, Addition/Subtraction)
M loops
Operand
A
x
Operand
Multiplier 0
B
2-15
Multiplier 1
Operand
A
Accumulator
Function implemented
x
Operand
in LatticeECP
B
Σ
LatticeECP/EC Family Data Sheet
Output
Operand
A
x
Operand
Multiplier
(k-1)
B
Architecture
loops
m/k