LFEC10E-3FN256C LATTICE SEMICONDUCTOR, LFEC10E-3FN256C Datasheet - Page 49

• Manufacturer Part Number: LFEC10E-3FN256C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3FN256C

• Package: 256FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 195
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
Derating Timing Tables
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case
numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be
much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and
voltage multiply the noted numbers with the derating factors provided below.
The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-
acteristics (Θ
The user must determine this temperature and then use it to determine the derating factor based on the following
derating tables: T
Table 3-5. Delay Derating Table for Internal Blocks
JA
), and the ambient temperature, as calculated with the following equation:
J
°C.
Commercial
T
J
—
—
25
85
0
°C
Industrial
T
T
105
-40
-25
J
20
45
JMAX
°C
= T
AMAX
1.14V
3-13
0.82
0.82
0.89
0.93
1.00
+ (Power * Θ
Power Supply Voltage
1.2V
0.77
0.76
0.83
0.87
0.94
JA
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
)
1.26V
0.71
0.71
0.78
0.81
0.89