PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 33

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

5.1
5.2
Table 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODE
Table 5-2 SUMMARY OF TRANSACTION ORDERING IN PCI-X MODE
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those
transactions cross PI7C21P100.
The following general ordering guidelines govern transactions crossing PI7C21P100:
ORDERING RULES
Table 5-1
Table 5-2 show the ordering relationships of all the transactions and refers by number to the
ordering rules that follow.
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read Completion
Delayed Write Completion
1. If the relaxed ordering bit is set in PCI to PCI mode, or the enable relaxed ordering bit in the primary and/or
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed or split requests is important, the initiator should not start a second
delayed or split transaction until the first one has been completed. If more than one
delayed or split transaction is initiated, the initiator should repeat all retried requests,
using some fairness algorithm. Repeating a delayed or split transaction cannot be
contingent on completion of another delayed transaction. Otherwise, a deadlock can
occur.
Write transactions flowing in one direction have no ordering requirements with respect to
write transactions flowing in the other direction. PI7C21P100 can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
The acceptance of a posted memory or memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master. This is
true for PI7C21P100 and must also be true for other bus agents. Otherwise, a deadlock
can occur.
PI7C21P100 accepts posted write transactions, regardless of the state of completion of
any delayed transactions being forwarded across PI7C21P100.
secondary data buffering control registers is set in any other mode, read completions can pass memory writes.
SUMMARY OF TRANSACTION ORDERING IN PCI MODE
Posted Write
No
No
No
No
No
Memory
Write
No
No
No
1
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Delayed
Read
Request
Yes
Yes
Yes
Yes
Yes
Split Read
Request
Yes
Yes
Yes
Delayed
Write
Request
Yes
Yes
No
Yes
Yes
Split Write
Request
Yes
Yes
No
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
Delayed
Read
Completion
Yes
Yes
Yes
Yes
Yes
Split Read
Completion
Yes
Yes
Yes
PI7C21P100
Delayed
Write
Completion
Yes
Yes
Yes
Yes
No
Split Write
Completion
Yes
Yes
Yes
and