PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 51

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

8.1.35
SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET
40h
BIT
31
30.28
27
26
25:24
23:22
21:20
19:16
FUNCTION
RESERVED
Maximum Memory
Read Byte Count
Enable Relaxed
Ordering
Secondary Special
Delayed Read Mode
Enable
Secondary Read
Prefetch Mode
Secondary Read Line
Prefetch Mode
Secondary Read
Multiple Prefetch Mode
RESERVED
TYPE
RO
RO
RW
RW
RW
RW
RW
RW
Page 51 of 77
DESCRIPTION
Reserved. Returns 0h when read.
Maximum Memory Read Byte Count
000: 512 bytes (default)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
101: 2048 bytes
110: 4096 bytes
111: 512 bytes
Maximum byte count is used by PI7C21P100 when generating read
requests on the primary interface in response to a memory read
operation initiated on the secondary interface which is in
conventional PCI mode and bits[9:8], bits[7:6], or bits[5:4] are set to
full prefetch.
Reset to 000
Relaxed Ordering Enable
0: Relaxed ordering is disabled in conventional PCI mode.
1: At the secondary interface, read completions that occur after the
first read completion are allowed to bypass posted writes and
complete with a higher priority in conventional PCI mode.
In PCI-X mode, the relaxed ordering bit in the attribute field will
take precedence. Reset to 0
Secondary Special Delayed Read Mode Enable
0: Retry any secondary master which repeats its transaction with
command code changes.
1: Allows any secondary master to change memory command code
(MR, MRL, MRM) after it has received a retry. PI7C21P100 will
complete the memory read transaction and return data back to the
primary bus master if the address and byte enables are the same.
This bit is ignored in PCI-X mode. Reset to 0
Secondary Read Prefetch Mode
00: One cache line prefetch if memory read address is in the
prefetchable range at the secondary interface
01: Reserved
10: Full prefetch if memory read address is in the prefetchable range
at the secondary interface.
11: Disconnect on the first DWORD.
These bits are ignored in PCI-X mode. Reset to 00
Secondary Read Line Prefetch Mode
00: One cache line prefetch if memory read line address is in
prefetchable range at the secondary interface
01: Reserved
10: Full prefetch if memory read multiple address is in prefetchable
range at the secondary interface
11: Reserved.
These bits are ignored if the secondary interface is in PCI-X mode.
Secondary Read Multiple Prefetch Mode
00: One cache line prefetch if memory read multiple address is in
prefetchable range at the secondary interface.
01: Reserved.
10: Full prefetch if memory read multiple address is in prefetchable
range at the secondary interface.
11: Reserved.
These bits are ignored if the secondary interface is in PCI-X mode.
Reset to 10.
Reserved. Returns 0000 when read.
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100