PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 48

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

8.1.26
8.1.27
8.1.28
8.1.29
8.1.30
8.1.31
8.1.32
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h
CAPABILITY POINTER – OFFSET 34h
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h
INTERRUPT LINE REGISTER – OFFSET 3Ch
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
31:0
BIT
15:0
BIT
31:16
BIT
7:0
BIT
31:0
BIT
7:0
BIT
15:8
FUNCTION
Prefetchable Limit
Upper 32-bit
FUNCTION
I/O Base Upper 16-bit
FUNCTION
I/O Limit Upper 16-bit
FUNCTION
Capability Pointer
FUNCTION
Expansion ROM Base
Address
FUNCTION
Interrupt Line Register
FUNCTION
Interrupt Pin Register
TYPE
TYPE
RW
TYPE
RW
TYPE
RO
TYPE
TYPE
RW
TYPE
RO
RW
RO
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DESCRIPTION
Specifies address bits[63:32] of the limit address for the address
range of prefetchable memory operations.
Reset to 0000 0000h
DESCRIPTION
Specifies address bits[31:16] of the base address for the address
range of I/O operations.
Reset to 0000h
DESCRIPTION
Specifies address bits[31:16] of the limit address for the address
range of I/O operations.
Reset to 0000h
DESCRIPTION
Pointer to a capabilities list in the configuration space. Returns 80h
when read.
DESCRIPTION
Expansion ROM not supported. Returns 00000000h when read
DESCRIPTION
For POST program to initialize to FFh, defining PI7C21P100 does
not implement an interrupt pin.
DESCRIPTION
Defines the interrupt pin, but PI7C21P100 does not implement any
interrupt pins. Read as 00h.
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100