PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 60

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

BIT
21
20
19
18
17
16
15:8
7:3
2:0
FUNCTION
Split Request Delayed
Split Completion
Overrun
Unexpected Split
Completion
Split Completion
Discarded
133MHz Capable
64-bit Device
Bus Number
Device Number
Function Number
TYPE
RW
RO
RO
RW
RW
RW
RO
RO
RO
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DESCRIPTION
Split Request Delayed
0: PI7C21P100 has not delayed a split request.
1: A split request moving toward the primary bus has been delayed
by PI7C21P100 because there is not enough room within the limit
specified in the split transaction commitment limit field in the
upstream split transaction control register.
Reset to 0
Split Completion Overrun
0: PI7C21P100 has accepted all split completions.
1: PI7C21P100 has terminated a split completion on the primary bus
with retry or disconnect at the next ADB because the buffers in the
bridge were full.
Reset to 0
Unexpected Split Completion
0: No unexpected split completion has been received.
1: An unexpected split completion has been received with the
requested ID equal to the bridge’s primary bus number, device
number, and function number on the bridge pirmary interface.
Reset to 0
Split Completion Discarded
0: No split completion has been discarded.
1: A split completion moving toward the primary bus has been
discarded by the bridge because the requester would not accept it.
Reset to 0.
133MHz Capable
Returns 1 when read to indicate PI7C21P100 is capable of 133MHz
operation on the primary interface.
64-bit Device
Returns a 1 when the AD interface is 64-bits wide on the primary bus
and P_REQ64#=0 at P_RST# de-assertion. Otherwise, AD interface
is 32-bits wide.
Bus Number
This is an additional address from which the contents of the primary
bus number register on type 1 configuration space header is read. The
bridge uses the bus number, device number, and function number
fields to create the completer ID when responding with a split
completion to a read of an internal bridge register. These fields are
also used for cases when one interface is in conventional PCI mode
and the other is in PCI-X mode.
Reset to 11111111
Device Number
The device number (AD[15:11]) of a type 0 configuration transaction
is assigned to the bridge by the connection of system hardware. Each
time the bridge is addressed by a configuration write transaction, the
bridge updates this register with the contents of AD[15:11] of the
address phase of the configuration transaction, regardless of which
register in the bridge is addressed by the transaction. The bridge is
addressed by a configuration write transaction if all of the following
are true:
- The transaction uses a configuration write command
- IDSEL is asserted during the address phase
- AD[1:0] are 00 (type 0 configuration transaction)
- AD[10:8] of the configuration address contain the appropriate
function number
Reset to 11111
Function Number
The function number (AD[10:8]) of the address of a type 0
configuration transaction to which the bridge responds.
Reset to 000
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100