PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 40

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
through the primary bus. Applications that do not require access to the bridge configuration
registers via the secondary bus should pull both the S_IDSEL and P_CFG_BUSY pins LOW.
7.8
SHORT TERM CACHING
Short Term Caching is a means to provide performance improvements where upstream
devices are not able to stream data continuously to meet the prefetching needs of the
PI7C21P100. When the master completes the transaction, the bridge is required to discard the
balance of any data that was prefetched for the master. To prevent performance impacts when
dealing with target devices that can only stream data of 128 to 512 bytes before
disconnecting, PI7C21P100 utilizes Short Term Caching. This feature applies only when the
secondary bus is operating in conventional PCI mode and provides a time limited read data
cache in which the bridge will not discard prefetched read data after the request has been
completed on the initiating bus. Short Term Caching is an optional feature which is enabled
by setting bit[8] and bit[15] offset B8h of the Miscellaneous Control Register 2. When
enabled, PI7C21P100 will not discard the additional prefetched data when the read transaction
has been completed on the initiating bus. PI7C21P100 will continue to prefetch data up to the
amount specified by bits [30:28] offset 40h of the Secondary Data Buffering Control Register.
Should the initiator generate a new transaction requesting the previously prefetched data,
PI7C21P100 will return that data. PI7C21P100 will discard the data approximately 64
secondary clocks after some of the data for a request has been returned to the initiator, and the
initiator has not requested additional data. This feature applies to all secondary devices if
enabled. System designers need to ensure that all attached devices have memory region(s) that
are architected to be accessed by only one master and that the additional prefetching will
present data to the initiator in the same state as if the initial transaction were continued. This
feature should only be used in system designs that are able to ensure that the data provided to
the master has not been modified since the initial transaction.
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July 5, 2005 Revision 1.07