PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 7

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

9
10
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12
9.1
9.2
9.3
9.4
9.5
10.1
10.2
10.3
10.4
8.1.36
8.1.37
8.1.38
8.1.39
8.1.40
8.1.41
8.1.42
8.1.43
8.1.44
8.1.45
8.1.46
8.1.47
8.1.48
8.1.49
8.1.50
8.1.51
8.1.52
8.1.53
8.1.54
8.1.55
8.1.56
8.1.57
8.1.58
8.1.59
8.1.60
8.1.61
8.1.62
8.1.63
8.1.64
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .................................................................. 65
ELECTRICAL INFORMATION.................................................................................................... 74
MECHANICAL INFORMATION.................................................................................................. 76
ORDERING INFORMATION........................................................................................................ 76
INSTRUCTION REGISTER .................................................................................................... 65
BYPASS REGISTER................................................................................................................ 65
DEVICE ID REGISTER ........................................................................................................... 65
BOUNDARY SCAN REGISTER............................................................................................. 66
JTAG BOUNDARY REGISTER ORDER ............................................................................... 66
MAXIMUM RATINGS ............................................................................................................ 74
DC SPECIFICATIONS............................................................................................................. 74
AC SPECIFICATIONS............................................................................................................. 74
POWER CONSUMPTION ....................................................................................................... 75
MISCELLANEOUS CONTROL REGISTER – OFFSET 44h........................................... 52
EXTENDED CHIP CONTROL REGISTER 1 – OFFSET 48h......................................... 52
EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h......................................... 53
ARBITER MODE REGISTER – OFFSET 50h................................................................. 53
ARBITER ENABLE REGISTER – OFFSET 54h.............................................................. 54
ARBITER PRIORITY REGISTER – OFFSET 58h ........................................................... 54
SERR# DISABLE REGISTER – OFFSET 5Ch ................................................................ 55
PRIMARY RETRY COUNTER REGISTER – OFFSET 60h............................................. 56
SECONDARY RETRY COUNTER REGISTER – OFFSET 64h....................................... 56
DISCARD TIMER CONTROL REGISTER – OFFSET 68h............................................. 57
RETRY AND TIMER STATUS REGISTER – OFFSET 6Ch ............................................ 57
OPAQUE MEMORY ENABLE REGISTER – OFFSET 70h ............................................ 57
OPAQUE MEMORY BASE REGISTER – OFFSET 74h ................................................. 58
OPAQUE MEMORY LIMIT REGISTER – OFFSET 74h ................................................ 58
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER – OFFSET 78h ....................... 58
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER – OFFSET 7Ch...................... 58
PCI-X CAPABILITY ID REGISTER – OFFSET 80h ....................................................... 58
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ........................................... 59
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h............................................. 59
PCI-X BRIDGE PRIMARY STATUS REGISTER – OFFSET 84h ................................... 59
SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ... 61
PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch .. 61
POWER MANAGEMENT ID REGISTER – OFFSET 90h............................................... 61
NEXT CAPABILITIES POINTER REGISTER – OFFSET 90h........................................ 62
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 90h.......................... 62
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h ......... 62
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h ................. 63
SECONDARY BUS PRIVATE DEVICE MASK REGISTER – OFFSET B0h................... 63
MISCELLANEOUS CONTROL REGISTER 2 – OFFSET B8h ....................................... 64
Page 7 of 77
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100